NXP Semiconductors PXN2020, Reference Manual, Page: 119 / 1376

PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 5-1
Chapter 5
System Clock Description
5.1 Introduction
This chapter describes the clock architecture and sources of the PXN20 system clocks.
The PXN20 has a number of different clock sources, serving various application requirements and
allowing maximum flexibility for the user application.
These are:
• High-frequency crystal oscillator described in Section 5.1.3, External High-Frequency Crystal
(4 – 40 MHz XTAL), supporting external crystals in the range of 4 – 40MHz. This is mainly used
as a precise clock source and PLL input clock source.
• Fast on-chip RC oscillator, described in Section 5.1.4, Internal High-Frequency RC Oscillator
(16 MHz_IRC). This is mainly used as the default clock source with fast startup, a fast clock source
in low-power modes, and for the watchdog timer.
• Slow on-chip RC oscillator, described in Section 5.1.5, Internal Low-Frequency RC Oscillator
(128 kHz_IRC). This is mainly used as an independent clock source for the ultra low power modes.
• 32 kHz crystal oscillator described in Section 5.1.6, External Low-Frequency Crystal
(32 kHz_XTAL), supporting an external crystal of 32 kHz. This is used for the Real Time Clock
applications and alternate clock source to the slow on-chip RC oscillator.
• Phase-locked loop, described in Section 5.1.7, FMPLL, supporting spread spectrum modulation to
reduce EMI and providing system frequencies above 40 MHz. This is mainly used in full run mode
and uses the high frequency crystal as its clock source. See
Chapter 7, Frequency Modulated
Phase-Locked Loop (FMPLL), for more information.
5.1.1 Features
The following list summarizes the system clock and clock generation on the PXN20:
• System clock can be derived from the following sources
— 4 – 40 MHz XTAL
— FMPLL
— 16 MHz IRC oscillator
• Programmable output clock divider of system clock (

1,

2,

4,

)
• Separate programmable peripheral bus clock divider ratio (

1,

2,

4,

) applied to system clock
• Frequency Modulated Phase-locked loop (FMPLL)
— Input clock frequency from 4 MHz to 40 MHz