NXP Semiconductors PXN2020, Reference Manual, Page: 1188 / 1376

Nexus Development Interface (NDI)
PXN20 Microcontroller Reference Manual, Rev. 1
36-38 Freescale Semiconductor
NOTE
The Nexus/JTAG Read/Write Access Control/Status Register (RWCS)
write (to begin a read access) or the write to the Read/Write Access Data
Register (RWD)(to begin a write access) does not actually begin its action
until one JTAG clock (TCK) after leaving the JTAG Update-DR state. This
prevents the access from being performed and therefore will not signal its
completion via the READY (RDY) output unless the JTAG controller
receives an additional TCK. In addition, EVTI is not latched into the device
unless there are clock transitions on TCK.
Therefore, the tool/debugger must provide at least one TCK clock for the
EVTI signal to be recognized by the MCU. When using the RDY signal to
indicate the end of a Nexus read/write access, ensure that TCK continues to
run for at least one TCK after leaving the Update-DR state. This can be just
a TCK with TMS low while in the Run-Test/Idle state or by continuing with
the next Nexus/JTAG command. Expect the affect of EVTI and RDY to be
delayed by edges of TCK. RDY is not available in all packages of all
devices.
36.6.8.6 Watchpoint Trigger Register (WT)
The watchpoint trigger register allows the watchpoints defined within the e200z6 Nexus1 logic to trigger
actions. These watchpoints can control program and/or data trace enable and disable. The WT bits can be
used to produce an address-related window for triggering trace messages. The WT register is shown in
Figure 36-20 and its fields are described in Table 36-27 .
Word@100 100 AHB[63:56] AHB[55:48] AHB[[47:40] AHB[39:32]
Doubleword@000 000
first RWD pass AHB[31:24] AHB[23:16] AHB[15:8] AHB[7:0]
second RWD pass AHB[63:56] AHB[55:48] AHB[[47:40] AHB[39:32]
Table 36-26. RWD data placement for Transfers
Transfer Size and
byte offset
RWA[2:0]
RWD
31:24 23:16 15:8 7:0