NXP Semiconductors PXN2020, Reference Manual, Page: 1173 / 1376

Nexus Development Interface (NDI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 36-23
has control of the TAP (see Section 35.4.4, JTAGC Instructions ). This allows the interface to all of these
individual TAP controllers to appear to be a single port from outside the device. Once a Nexus module has
ownership of the TAP, that module acts like a single-bit shift register, or bypass register, if no register is
selected as the shift path.
36.5.5.2.6 MCKO
MCKO is an output clock to the development tools used for the timing of MSEO and MDO pin functions.
MCKO is derived from the system clock and its frequency is determined by the value of the
MCKO_DIV[2:0] field in the PCR. Possible operating frequencies include full, one-half, one-quarter, and
one-eighth SYS_CLK speed. MCKO is enabled by setting the MCKO_EN bit in the PCR.
The NPC also controls dynamic MCKO clock gating. The setting of the MCKO_GT bit inside the PCR
determines whether or not MCKO gating control is enabled. The MCKO_GT bit resets to a logic 0. In this
state gating of MCKO is disabled. To enable gating of MCKO, the MCKO_GT bit in the PCR is written
to a logic 1. When MCKO gating is enabled, MCKO is driven to a logic 0 if the auxiliary port is enabled
but not transmitting messages and there are no pending messages from Nexus clients.
36.5.5.2.7 EVTO Sharing
The NPC controls sharing of the EVTO output between all Nexus clients that produce an EVTO signal.
EVTO is driven for one MCKO period whenever any module drives its EVTO. The sharing mechanism is
a logical AND of all incoming EVTO signals from Nexus blocks, thereby asserting EVTO whenever any
block drives its EVTO. The order these signals are connected at the NPC input does not matter. When no
MCKO is active, such as in disabled mode, the NPC assumes an MCKO frequency of one-half system
clock speed when driving EVTO. EVTO sharing is active as long as the NPC is not in reset.
36.5.5.2.8 Nexus Reset Control
The JCOMP input that is used as the primary reset signal for the NPC is also used by the NPC to generate
a single-bit reset signal for other Nexus blocks. If JCOMP is negated, an internal reset signal is asserted,
indicating that all Nexus modules should be held in reset. This internal reset signal is also asserted during
a power-on-reset. The single bit reset signal functions much like the IEEE 1149.1-2001 defined TRST
signal and allows JCOMP reset information to be provided to the Nexus blocks without each block having
to sense the JCOMP signal directly.
36.5.5.2.9 Processor Status (PSTAT) Muxing
PSTAT mode is intended for factory processor debug only.
36.5.6 NPC Initialization/Application Information
To initialize the TAP for NPC register accesses, the following sequence is required:
1. Enable the NPC TAP controller. This is achieved by asserting JCOMP and loading the
ACCESS_AUX_TAP_NPC instruction in the JTAGC.
2. Load the TAP controller with the NEXUS-ENABLE instruction.