NXP Semiconductors PXN2020, Reference Manual, Page: 1137 / 1376

IEEE 1149.1 Test Access Port Controller (JTAGC)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 35-3
Figure 35-2. JTAG/Nexus Daisy Chain of the PXN20 e200z6 and e200z0 Cores
35.1.2 Features
The JTAGC is compliant with the IEEE 1149.1-2001 standard and has these major features:
• IEEE 1149.1-2001 test access port (TAP) interface.
• A JCOMP input that provides the ability to share the TAP.
• A 5-bit instruction register that supports several IEEE 1149.1-2001 defined instructions, as well as
several public and private MCU-specific instructions (see
Table 35-2 ).
• Three test data registers: a bypass register, a boundary scan register, and a device identification
register.
• A TAP controller state machine that controls the operation of the data registers, instruction register,
and associated circuitry.
35.1.3 Modes of Operation
The JTAGC uses JCOMP and a power-on reset indication as its primary reset signals. Several IEEE
1149.1-2001 defined test modes are supported, as well as a bypass mode.
TDO
e200z6 OnCE TAP
TDI
TDI TDO
TDO TDI
e200z0 OnCE TAP
NPC/JTAGC
ACCESS_AUX_TAP_Z6 (from _ONCE) ACCESS_AUX_TAP_MULTI ACCESS_AUX_TAP_Z0
Multi-core access
Single-core access
TMS and JCOMP are not shown for clarity.
NPC TAP also not shown for clarity.