NXP Semiconductors PXN2020, Reference Manual, Page: 1098 / 1376

Analog-to-Digital Converter (ADC)
PXN20 Microcontroller Reference Manual, Rev. 1
34-18 Freescale Semiconductor
34.3.2.13 DMA Enable Register (DMAE)
The DMAE register sets up the DMA for use with the ADC.
NOTE
The ADC_DMAE[DCLR] should not be used. When
ADC_DMEAE[DCLR] is set the DMA request should be cleared only after
the data registers are read. However, the DMA request is automatically
cleared and will not be recognised by the eDMA.
34.3.2.14 DMA Channel Select Register 0 (DMAR0)
The DMAR0 register contains the DMA Enable bits for group 0 channels (channels 0–31).
Address: AD 0x0040 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DCLR
DMA
EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 34-14. DMA Enable Register (DMAE)
Table 34-14. DMAE Field Descriptions
Field Description
DCLR DMA Clear sequence enable.
0 DMA request cleared by Acknowledge from DMA controller.
1 DMA request cleared on read of data registers.
DMAEN DMA global enable.
0 DMA feature is disabled.
1 DMA feature is enabled.