NXP Semiconductors PXN2020, Reference Manual, Page: 1060 / 1376

Inter-Integrated Circuit Bus Controller Module (I
2
C)
PXN20 Microcontroller Reference Manual, Rev. 1
32-16 Freescale Semiconductor
32.5 Initialization/Application Information
32.5.1 I
2
C Programming Examples
32.5.1.1 Initialization Sequence
Reset puts the I
2
C bus control register in its default state. Before the interface can be used to transfer serial
data, an initialization procedure must be carried out, as follows:
1. Update the frequency divider register (IBFD) and select the required division ratio to obtain SCL
frequency from system clock.
2. Update the I
2
C bus address register (IBAD) to define its slave address.
3. Clear the MDIS bit of the I
2
C bus control register (IBCR) to enable the I
2
C interface system.
4. Modify the bits of the IBCR to select master/slave mode, transmit/receive mode and interrupt
enable or not. Optionally modify the bits of the I
2
C bus interrupt configuration register (IBIC) to
further refine the interrupt behavior.
5. Configure the SDA and SCL pads. (The SIU Pad Configuration registers must be configured to
select the appropriate I
2
C function. Also, the open drain feature of the pad must be enabled by
setting the ODE bit in the appropriate SIU pad configuration register.)
32.5.1.2 Generation of START
After completion of the initialization procedure, serial data can be transmitted by selecting the master
transmitter mode. If the device is connected to a multi-master bus system, the state of the I
2
C bus busy bit
(IBB) must be tested to check if the serial bus is free.
If the bus is free (IBB = 0), the start condition and the first byte (the slave address) can be sent. The data
written to the data register comprises the slave calling address and the LSB, which is set to indicate the
direction of transfer required from the slave.
The bus free time (i.e., the time between a STOP condition and the following START condition) is built
into the hardware that generates the START cycle. Depending on the relative frequencies of the system
clock and the SCL period, it may be necessary to wait until the I
2
C is busy after writing the calling address
to the IBDR before proceeding with the following instructions. This is illustrated in the following example.
An example of the sequence of events which generates the START signal and transmits the first byte of
data (slave address) is shown below:
while (bit 2, IBSR ==1) // wait in loop for IBB flag to clear
bit3 and bit 2, IBCR = 1 // set transmit and master mode, i.e. generate start condition
IBDR = calling_address // send the calling address to the data register
while (bit 2, IBSR ==0) // wait in loop for IBB flag to be set
32.5.1.3 Post-Transfer Software Response
Transmission or reception of a byte sets the data transferring bit (TCF) to 1, which indicates one byte
communication is finished. The I
2
C Bus interrupt bit (IBIF) is set also; an interrupt is generated if the