NXP Semiconductors
UM10858
PN7462 family HW user manual
UM10858
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User manual
COMPANY PUBLIC
Rev. 1.4 — 14 May 2018
314514
92 of 345
Table 85. PCR_CLK_CFG2_REG (address offset 0x34)
Bit
Symbol
Access
Value
Description
31:18
RESERVED
rw
0x00
Reserved
19
CTRL_TXLDO_CLK
rw
0x00
TXLDO clock division select. 0->LFO/2 , 1-> LFO
18
EXT_CLK_SEL
rw
0x00
Selects between XTAL clock and external clock.
0 - XTAL
1: external clock
17:16
HSUART_IP_CLKSEL
rw
0x00
Selects ip clock divider value for hsuart.
00: xtal/1
01: xtal/2
10: xtal/4
11: RESERVED
15:14
SPIM_IP_CLKSEL
rw
0x00
Selects ip clock divider value for spim.
00: xtal/1
01: xtal/2
10: xtal/4
11: RESERVED
13:12
I2CM_IP_CLKSEL
rw
0x00
Selects ip clock divider value for spim.
00: xtal/1
01 -.xtal/2
10: xtal/4
11: RESERVED
11
CTSEQ_CLKSEL
rw
0x01
0: +10
1: +82
10
EE_EEPROM_CLKSEL
rw
0x01
Selects the divider value for the lfo clock for the
EEPROM module
0: LFO/1
1: lfo/4
9
EE_PF_FIX_CLKSEL
rw
0x01
Selects between divided xtal value
0: No clock
1: xtal-clk/32
8:6
EE_PF_VAR_CLKSEL
rw
0x04
Selects between and xtal divided clocks for page flash
module.
0: No clock
1: Xtal-clk/4
2: Xtal-clk/8
3: Xtal-clk/16
4: Xtal-clk/32
5: 7 RESERVED
5:4
SPARE_CELL_CLK_CFGL
rw
0x00
Spare cells to be used for clock config.
3:2
RESERVED
rw
0x00
Reserved
1:0
SYSTEM_CLOCK_SEL
rw
0x00
Selects the divider for the system clock.
00: Divby1
