NXP Semiconductors
UM10858
PN7462 family HW user manual
UM10858
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© NXP B.V. 2018. All rights reserved.
User manual
COMPANY PUBLIC
Rev. 1.4 — 14 May 2018
314514
73 of 345
These reset sources trigger the reset generator that generates a global reset pulse. The
Reset Generator is active high-level sensitive to the reset sources. As long as one reset
source is high, the global reset will be active. After releasing the reset source, the reset
pulse will be prolonged to at least one cycle. The power-on reset sequence is asserted
when the device is powered up. It is used to keep the system in reset state until proper
supply conditions are established. This point is achieved when the internal supply voltage
reaches 1.55 V.
When the internal reset is removed, the processor begins executing at address 0, which
is initially the reset vector mapped from the boot block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
8.2 Boot reason decoding
Table 67. Boot reason decoding
PCR_STATUS.boot_reason Values
reflected in
register
Description
startup_por
0
Analog Reset Sources (Startup Por or leave
from HPD or VEN)
Rfld
1
RF Level Detector wakeup
wuc_cnt
2
Wakeup Timer
int_aux
3
Contact uart int_aux pad gives an interrupt
Ct
4
Contact card presence is detected
i2c
5
I2C address detected
RESERVED
6
Reserved
Spi
7
SPI slave received transaction
usb_resume
8
USB Resume signaling from Host
soft_reset
9
Soft reset given by software
Wdog
10
Watch dog timer timeout or ARM reset
Tvddmon
11
5V detected by TVDD monitor
hif_reset
12
VEN from low to high back (only for test
purpose) Ii2c slave or smb slave requested for
reset
temp0
13
Neg-edge detected for Temperature error from
temperature sensor 0
temp1
14
Neg-edge detected for Temperature error from
temperature sensor 1
no_pvdd
15
PVDD dropped
pvdd_ilim
16
Pvdd current limiter input has become 0
1
gpio
17
Gpio interrupt
hsu
18
HSUART transaction detected
