NXP Semiconductors
UM10858
PN7462 family HW user manual
UM10858
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© NXP B.V. 2018. All rights reserved.
User manual
COMPANY PUBLIC
Rev. 1.4 — 14 May 2018
314514
66 of 345
Bit
Symbol
Access Value
Description
9
USB_PLL_PREQ
R/W
0x00
USB_PLL post-divider ratio change request
1: Request change of USB_PLL post-divider ratio (ratio
taken from register)
8
USB_PLL_NREQ
R/W
0x00
USB_PLL pre-divider ratio change request
1: Request change of USB_PLL pre-divider ratio (ratio
taken from register)
7
USB_PLL_MREQ
R/W
0x00
USB_PLL feedback divider ratio change request
1: Request change of USB_PLL feedback divider ratio
(ratio taken from register)
6
USB_PLL_FRM
R/W
0x00
USB_PLL free running mode
1: Enable free running mode of USB PLL
5
USB_PLL_SKEW_EN
R/W
0x00
USB_PLL skew mode
1: Enable skew mode of USB_PLL
4
USB_PLL_DIRECTO
R/W
0x00
Bypass of the USB_PLL post-divider
1: Enable Bypass of USB_PLL post-divider
0: USB_PLL post-divider Bypass disable
3
USB_PLL_DIRECTI
R/W
0x00
Bypass of the USB_PLL pre-divider
1: Enable Bypass of USB_PLL pre-divider
0: USB_PLL pre-divider Bypass disable
2
USB_PLL_BYPASS
R/W
0x00
Bypass of the USB_PLL (clkout=clkin)
1: Enable Bypass of USB_PLL
0: USB_PLL Bypass disable
1
USB_PLL_CLKEN
R/W
0x00
Enable the USB_PLL output clock
1: Enable output clock from USB PLL
0: Disable output clock from USB PLL
0
USB_PLL_PD
R/W
0x01
USB_PLL Into power down
1: USB PLL powered down
0: USB PLL powered up
7.6.2 PLL M decoded divider ratio
The CLKGEN_USB_PLL_MDEC_WO_SOFTDEC_REG register contains the USB PLL
multiplier and divider values. Changes to
CLKGEN_USB_PLL_MDEC_WO_SOFTDEC_REG register do not take effect until a
correct USB feed sequence has been given (see
Section 7.2
). Calculations for the USB
PLL frequency, and multiplier and divider values are found in
Section 7.2
Table 58. CLKGEN_USB_PLL_MDEC_WO_SOFTDEC_REG (address 0010h)
Bit
Symbol
Access
Value
Description
31:17
RESERVED
R/W
0x00
Reserved
16:0
USB_MDEC_WO_SOFTDEC
R/W
0x00
divider ratio code for M-divider when soft decoder is
not used
