NXP Semiconductors PN7360AUEV, User Manual

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NXP Semiconductors
UM10858
PN7462 family HW user manual
UM10858 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
User manual
COMPANY PUBLIC Rev. 1.4 — 14 May 2018
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7.5 Clock Status Register description
Table 52. CLKGEN_STATUS_REG (address 0000h)
Bit Symbol Access Value Description
31:27 RESERVED - 0 Reserved
26 CLIF_CLOCK_PRESENCE_OK R 0 Indicates the status of clkgen_clif_pll_lock2_o signal.
1: CLIF PLL2 lock signal set
0: CLIF PLL2 lock signal not set
25 XTAL_ACTIVATION_TIME
OUT_ERROR R 0 high if timeout for XTAL Activation is reached
1: Xtal activation has timed-out
24 XTAL_DETECT_OK R 0
Indicates the presence of clock signal on clk_xtal if
xtal_detect_enable is set.
1: Xtal detection done
23 XTAL_OSC_OK R 0
high to indicate the clock is ready
1: Xtal osc clock is ready
22 CLIF_PLL_LOCK_OVERRIDEN R 0
1: pll_lock2 OR pll_bypass_lock2 is set
0: pll_lock2 OR pll_bypass_lock2 is not set
21 CLIF_CLK_IN_DETECT_DONE R 0 CLIF PLL detection status
1: CLIF PLL clk_in detection done
20 CLIF_CLK_IN_OK R 0 PLL input clock detector ok signal.
1: clk_in is present and correct
0: clk_in not ok
19 CLIF_PLL_LOCK2 R 0
Lock detector Output for 2nd PLL
1: PLL2 lock is set
0: PLL2 lock is not set
18 CLIF_PLL_LOCK1 R 0 Lock detector Output for 1st PLL.
1: PLL1 lock is set
0: PLL1 lock is not set
17 XTAL_OK R 0 1: XTAL oscillator is activated
16 XTAL_ENABLED R 0 1: XTAL oscillator is enabled
0: XTAL oscillator disabled
15:8 CLK_IN_EDGES_COUNTER R 0 input clock edges counter value when the
USB_PLL_CLK_IN detection completes successfully
7 CLK_IN_DETECT_DONE R 0 USB_PLL input clock detection status
1: USB PLL input clock detection completed
6 CLK_IN_OK R 0 USB_PLL input clock detector OK Status.
1: CLK_IN is present and the frequency matches
expected frequency
5 USB_PLL_FR R 0 USB_PLL free running detector status
1: USB PLL is in free running mode
4 USB_PLL_PACK R 0 USB_PLL post-divider ratio change acknowledge
1: USB_PLL post-divider ratio change has been
Acknowledged
0: No post-divider ratio change
3 USB_PLL_NACK R 0 USB_PLL pre-divider ratio change acknowledge
1: USB_PLL pre-divider ratio change has been
Acknowledged
0: No pre-divider ratio change
2 USB_PLL_MACK R 0 USB_PLL feedback divider ratio change acknowledge
1: USB_PLL feedback divider ratio change has been