NXP Semiconductors
UM10858
PN7462 family HW user manual
UM10858
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© NXP B.V. 2018. All rights reserved.
User manual
COMPANY PUBLIC
Rev. 1.4 — 14 May 2018
314514
127 of 345
11. General-purpose timers and watchdog timers
The PN7462 family includes two 12-bit general purpose timers (on LFO clock domain)
with match capabilities two 32-bit general purpose timers (on HFO clock domain) and a
Watch Dog Timer (WDT).
The purpose of the watchdog is to reset the microcontroller within a reasonable amount
of time if it enters an erroneous state. When enabled, the watchdog will generate a
system reset if the user program fails to ‘feed’ (or reload) the watchdog within a
predetermined amount of time.
The timers and watchdog are software configurable via a 32-bit APB slave interface.
Table 148. Timer characteristics
Name
Clock
source
Frequency
Counter
length (bit)
Resolution
(ms)
Max
delay(s)
Chaining
possible
Timer 0
LFO/2
190 KHz
12
300 us
1.2
no
Timer 1
LFO/2
190 KHz
12
300 us
1.2
yes
Timer 2
HFO
20 MHz
32
50 ns
214
no
Timer 3
HFO
20 MHz
32
50 ns
214
no
Watchdog
LFO/128
2.96 KHz
10
21.5 ms
22
no
11.1 Timers features (Timers 0 and 1)
•
Two 12-bit counters
•
1 match register per timer, no capture registers and capture trigger pins are needed
•
1 common output line gathering the four timer (Timer0, Timer1, Timer2, Timer3)
Interrupts
•
Timer0 and Timer1 can be concatenated (multiplied)
•
Timer0 and Timer1 have two count modes: single-shot or free-running
•
Timer0 and Timer1 timeout interrupts can be individually masked
•
Timer0 and Timer1 Clock source is LFO clock
11.2 Timers features (Timer 2 and 3)
•
Two 32-bit counters
•
match register per timer, no capture registers and capture trigger pins are needed
•
1 common output line gathering the four timer (Timer0, Timer1, Timer2, Timer3)
Interrupts
•
Timer2 and Timer3 have two count modes: single-shot or free-running
•
Timer2 and Timer3 timeout interrupts can be individually masked
•
Timer2 and Timer3 clock source is HFO Clock
11.3 Watchdog features
•
The watchdog has 10-bit counter
