NXP Semiconductors PN7360AUEV, User Manual

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NXP Semiconductors
UM10858
PN7462 family HW user manual
UM10858 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
User manual
COMPANY PUBLIC Rev. 1.4 — 14 May 2018
314514
104 of 345
Bit Symbol Access Value Description
0
CT_ENABLE_PUP r- 0x00
Value of ct_pres_enable_pup_i coming from CTIF is
latched and is used to detect card activity during standby
and suspend modes if CTIF is enabled as wakeup
source
1: CT pres pull up enabled
Table 115. PCR_HOSTIF_SAVE1_REG (address offset 0xBC)
Bit Symbol Access Value Description
31:11 RESERVED rw 0x00 Reserved
10 HSU_TX_DIVIDER rw 0x00 TX divider save (only save reg for stby)
9:0 HSU_RX_DIVIDER rw 0x00 RX Divider save (only save reg for stby)
Table 116. PCR_HOSTIF_SAVE2_REG (address offset 0xC0)
Bit Symbol Access Value Description
31:24 RESERVED rw 0x00 Reserved
23:11 HSU_TX_CLK_CORRECT rw 0x00 clock correction for TX (only save reg for stby)
10:0 HSU_RX_CLK_CORRECT rw 0x00 Clock correction for RX (only save reg for stby)
Table 117. PCR_TXLDO_MON_REG (address offset 0xC4)
Bit Symbol Access Value Description
31:4 RESERVED rw 0x00 Reserved
3 WELL_MNGT rw 0x01 TXLDO well mngt
2
SRC_5V_MONITOR rw 0x00
Input of the 5 V monitor.
1: TVDD is the source of 5 V monitor
0: VUP_TX is the source of 5 V monitor
1
THRES_5V_MONITOR rw 0x00
Comparator threshold selector
1: Threshold of 5 V Monitor is 5 V
0
EN_5V_MONITOR rw 0x00
1: Enable the 5 V monitor on TVDD
0: Disable the 5 V monitor on TVDD
Table 118. PCR_BOOT2_REG (address offset 0xC8)
Bit Symbol Access Value Description
31:24 SPARE_CELL3 rw 0x00 Third set of spare cells.
23 BOOT_REASON_ACTIVE_
HPD
r- 0x00 1: Boot because of coming out of ACTIVE_HPD
22
BOOT_REASON_VBUS_L
OW
r- 0x00
1: Boot because of VBUS going low in suspend or
standby.
21:0 SPARE_CELL2 rw 0x00000 Second set of space cells