NXP Semiconductors PN544 C2, User Manual, Page: 141 / 172

NXP Semiconductors
UM191812
PN544 C2 User Manual
191812 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
User Manual Rev. 1.2 — 2010-06-16 141 of 172
9.17 GPIO(s)
The host can change the G eneral P urpose I nput O utput pins configuration
•
* Either by accessing directly the hardware registers (in that case the configuration
will be lost after a power down)
•
* Or by setting some EEPROM areas. The EEPROM values will be loaded in the chip
at power up.
•
There are 8 GPIOs named GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6 and
GPIO7. Some of them can have a special function:
GPIO1 is Clock acknowledge when Clock acknowledge by pin is used (see chapter
“
Acknowledge through CLKACK pin ”).
GPIO2 is Clock request when Clock acknowledge by pin is used or Power request when
Power request is used (see chapter “
Request through CLKREQ pin ” and parameter
SwpMgt_Request_Power in chapter “ SWP configuration ”).
GPIO3 is Power request when Power request is used (see parameter
SwpMgt_Request_Power in chapter “
SWP configuration ”).
GPIO4 is used at boot to possibly enter the Download mode (see paragraph
“Download”).
GPIO5 has to be kept HIGH during PN544 boot.
The default configuration of the GPIOs port is described in [7].
The PN544 NXP_READ and NXP_WRITE commands (see $ HCI Proprietary gate
‘PN544Mgt’) can be used to change the default configuration of the GPIOs (directly in the
hardware registers or in EEPROM).
9.17.1 GPIO Direct Hardware register access
See chapter “ PN544 register access / GPIO settings ”
9.17.2 GPIO EEPROM settings access
See ‘0 chapter.
9.17.3 Examples
In the following descriptions, “permanently” means that the change is applied in
EEPROM. Therefore the new value is only applied at next power up.