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UM10310_1

© NXP B.V. 2008. All rights reserved.

User manual

Rev. 01 — 1 December 2008

129 of 139

NXP Semiconductors

UM10310

P89LPC9321 User manual

18.19 Boot Vector register

18.20 Boot status register

Table 117. Sector Security Bytes (SECx) bit description

Bit Symbol

Description

0

MOVCDISx

MOVC Disable. Disables the MOVC command for sector x. Any MOVC that attempts to read a byte in a
MOVC protected sector will return invalid data. This bit can only be erased when sector x is erased.

1

SPEDISx

Sector Program Erase Disable x. Disables program or erase of all or part of sector x. This bit and sector
x are erased by either a sector erase command (ISP, IAP, commercial programmer) or a 'global' erase
command (commercial programmer).

2

EDISx

Erase Disable ISP. Disables the ability to perform an erase of sector x in ISP or IAP mode. When
programmed, this bit and sector x can only be erased by a 'global' erase command using a commercial
programmer. This bit and sector x CANNOT be erased in ISP or IAP modes.

3:7 -

reserved

Table 118. Effects of Security Bits

EDISx

SPEDISx

MOVCDISx

Effects on Programming

0

0

0

None.

0

0

1

Security violation flag set for sector CRC calculation for the specific sector.
Security violation flag set for global CRC calculation if any MOVCDISx bit is set.
Cycle aborted. Memory contents unchanged. CRC invalid. Program/erase
commands will not result in a security violation.

0

1

x

Security violation flag set for program commands or an erase page command.
Cycle aborted. Memory contents unchanged. Sector erase and global erase are
allowed.

1

x

x

Security violation flag set for program commands or an erase page command.
Cycle aborted. Memory contents unchanged. Global erase is allowed.

Table 119. Boot Vector (BOOTVEC) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

-

-

-

BOOTV4

BOOTV3

BOOTV2

BOOTV1

BOOTV0

Factory default
value

0

0

0

1

1

1

1

1

Table 120. Boot Vector (BOOTVEC) bit description

Bit Symbol

Description

0:4 BOOTV[0:4]

Boot vector. If the Boot Vector is selected as the reset address, the P89LPC9321 will start execution at
an address comprised of 00h in the lower eight bits and this BOOTVEC as the upper eight bits after a
reset.

5:7 -

reserved

Table 121. Boot Status (BOOTSTAT) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

DCCP

CWP

AWP

-

-

-

-

BSB

Factory default
value

0

0

0

0

0

0

0

1

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Summary of Contents for P89LPC9321 UM10310

Page 1: ...UM10310 P89LPC9321 User manual Rev 01 1 December 2008 User manual Document information Info Content Keywords P89LPC9321 Abstract Technical information for the P89LPC9321 device...

Page 2: ...008 2 of 139 Contact information For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com NXP Semiconductors UM10310 P89LPC9321 User...

Page 3: ...es the rate of standard 80C51 devices Many system level functions have been incorporated into the P89LPC9321 in order to reduce component count board space and system cost 1 1 Pin configuration Fig 1...

Page 4: ...7 ICA P2 6 OCA P0 1 CIN2B KBI1 P0 2 CIN2A KBI2 P0 3 CIN1B KBI3 P0 4 CIN1A KBI4 P0 5 CMPREF KBI5 VDD P0 6 CMP1 KBI6 P0 7 T1 KBI7 P1 2 T0 SCL P2 2 MOSI P2 3 MISO P2 4 SS P2 5 SPICLK P1 1 RXD P1 0 TXD P...

Page 5: ...Port 0 bit 3 High current source I CIN1B Comparator 1 positive input B I KBI3 Keyboard input 3 P0 4 CIN1A KBI4 23 I O P0 4 Port 0 bit 4 High current source I CIN1A Comparator 1 positive input A I KBI4...

Page 6: ...ress 0 Also used during a power on sequence to force ISP mode P1 6 OCB 5 I O P1 6 Port 1 bit 6 High current source O OCB Output Compare B P1 7 OCC 4 I O P1 7 Port 1 bit 7 High current source O OCC Out...

Page 7: ...chmitt triggered inputs Port 3 also provides various special functions as described below P3 0 XTAL2 CLKOUT 9 I O P3 0 Port 3 bit 0 O XTAL2 Output from the oscillator amplifier when a crystal oscillat...

Page 8: ...10 P89LPC9321 User manual 1 3 Functional diagram Fig 4 Functional diagram VDD VSS PORT 0 PORT 3 TXD RXD T0 INT0 INT1 RST SCL SDA 002aae103 CMP2 CIN2B CIN2A CIN1B CIN1A CMPREF CMP1 T1 XTAL2 XTAL1 KBI0...

Page 9: ...LE OSCILLATOR DIVIDER CPU clock CONFIGURABLE OSCILLATOR ON CHIP RC OSCILLATOR WITH CLOCK DOUBLER internal bus POWER MONITOR POWER ON RESET BROWNOUT RESET 002aae102 UART ANALOG COMPARATORS 512 BYTE AUX...

Page 10: ...SFR locations not defined Accesses to any defined SFR locations must be strictly for the functions for the SFRs SFR bits labeled 0 or 1 can only be written and read as follows Unless otherwise specif...

Page 11: ...0000 0000 AUXR1 Auxiliary function register A2H CLKLP EBRR ENT1 ENT0 SRST 0 DPS 00 0000 00x0 Bit address F7 F6 F5 F4 F3 F2 F1 F0 B B register F0H 00 0000 0000 BRGR0 2 Baud rate generator 0 rate low B...

Page 12: ...by M control 95H 00 0000 0000 DPTR Data pointer 2 bytes DPH Data pointer high 83H 00 0000 0000 DPL Data pointer low 82H 00 0000 0000 FMADRH Program flash address high E7H 00 0000 0000 FMADRL Program...

Page 13: ...ure A register high ABH 00 0000 0000 ICRAL Input capture A register low AAH 00 0000 0000 ICRBH Input capture B register high AFH 00 0000 0000 ICRBL Input capture B register low AEH 00 0000 0000 Bit ad...

Page 14: ...register 86H 00 0000 0000 KBPATN Keypad pattern register 93H FF 1111 1111 OCRAH Output compare A register high EFH 00 0000 0000 OCRAL Output compare A register low EEH 00 0000 0000 OCRBH Output compar...

Page 15: ...output mode 1 91H P1M1 7 P1M1 6 P1M1 4 P1M1 3 P1M1 2 P1M1 1 P1M1 0 D3 1 11x1 xx11 P1M2 Port 1 output mode 2 92H P1M2 7 P1M2 6 P1M2 4 P1M2 3 P1M2 2 P1M2 1 P1M2 0 00 1 00x0 xx00 P2M1 Port 2 output mode...

Page 16: ...99H xx xxxx xxxx Bit address 9F 9E 9D 9C 9B 9A 99 98 SCON Serial port control 98H SM0 FE SM1 SM2 REN TB8 RB8 TI RI 00 0000 0000 SSTAT Serial port extended status register BAH DBMOD INTLO CIDIS DBISEL...

Page 17: ...ter E9H TOIF2 TOCF2D TOCF2C TOCF2B TOCF2A TICF2B TICF2A 00 0000 0x00 TISE2 CCU interrupt status encode register DEH ENCINT 2 ENCINT 1 ENCINT 0 00 xxxx x000 TL0 Timer 0 low 8AH 00 0000 0000 TL1 Timer 1...

Page 18: ...is unpredictable 3 The RSTSRC register reflects the cause of the UM10310 reset except BOIF bit Upon a power up reset all reset source flags are cleared except POF and BOF the power on reset value is...

Page 19: ...The reset value of CLKCON 2 to CLKCON 0 come from UCFG1 2 to UCFG1 0 and reset value of CLKDBL bit comes from UCFG2 7 4 On power on reset and watchdog reset the PGAxTRIM8X16X and PGAxTRIM2X4X registe...

Page 20: ...implemented on chip The P89LPC9321 has 512 bytes of on chip XDATA memory plus extended SFRs located in XDATA CODE 64 kB of Code memory space accessed as part of program execution and via the MOVC ins...

Page 21: ...doubler option when enabled provides an output frequency of 14 746 MHz PCLK Clock for the various peripheral devices and is CCLK 2 2 2 1 Oscillator Clock OSCCLK The P89LPC9351 provides several user se...

Page 22: ...egister This can be done by reading the contents of the TRIM register into the ACC for example modifying bit 6 and writing this result back into the TRIM register Alternatively the ANL direct or ORL d...

Page 23: ...ription 0 TRIM 0 Trim value Determines the frequency of the internal RC oscillator During reset these bits are loaded with a stored factory calibration value When writing to either bit 6 or bit 7 of t...

Page 24: ...drive levels This is especially important for low frequency crystals see text Fig 8 Block diagram of oscillator control 2 002aae108 RTC CPU WDT DIVM CCLK UART OSCCLK I2C BUS PCLK TIMER 0 AND TIMER 1 H...

Page 25: ...dividing the clock the CPU can retain the ability to respond to events other than those that can cause interrupts i e events that allow exiting the Idle mode by executing its normal program at a lowe...

Page 26: ...down mode 3 1 Interrupt priority structure There are four SFRs associated with the four interrupt levels IP0 IP0H IP1 IP1H Every interrupt has two bits in IPx and IPxH x 0 1 and can therefore be assig...

Page 27: ...data sheet Dynamic characteristics for glitch filter specifications However pins SDA INT0 P1 3 and SCL T0 P1 2 do not have the glitch suppression circuits Therefore INT1 has glitch suppression while...

Page 28: ...160 IE0 EX0 IE1 EX1 BOIF EBO KBIF EKBI interrupt to CPU wake up if in power down EWDRT CMF2 CMF1 EC EA IE0 7 TF1 ET1 TI RI RI ES ESR TI EST SI EI2C SPIF ESPI RTCF ERTC RTCCON 1 WDOVF TF0 ET0 any CCU i...

Page 29: ...floating A second pull up called the weak pull up is turned on when the port latch for the pin contains a logic 1 and the pin itself is also at a logic 1 level This pull up provides the primary sourc...

Page 30: ...a port configured in this manner must have an external pull up typically a resistor tied to VDD The pull down for this mode is the same as for the quasi bidirectional mode The open drain port configur...

Page 31: ...port latch contains a logic 1 The push pull mode may be used when more source current is needed from a port output The push pull port configuration is shown in Figure 13 A push pull port pin has a Sch...

Page 32: ...only or open drain Every output on the P89LPC9321 has been designed to sink typical LED drive current However there is a maximum total output current for all ports which must not be exceeded Please r...

Page 33: ...nt Table 15 gives BOD trip points configuration In total power down mode PMOD1 PMOD0 11 the circuitry for the Brownout Detection is disabled for lowest power consumption When PMOD1 PMOD0 not equal to...

Page 34: ...til cleared by software by writing a logic 0 to the bit BOF RSTSRC 5 will be set when POF is set 5 3 Power reduction modes The P89LPC9321 supports three different power reduction modes as determined b...

Page 35: ...mediately and begin execution when the oscillator is stable Oscillator stability is determined by counting 1024 CPU clocks after start up when one of the crystal oscillator configurations is used or 2...

Page 36: ...e UART When logic 0 the Timer 1 overflow rate is divided by two before being supplied to the UART See Section 9 Table 20 Power Control register A PCONA address B5h bit allocation Bit 7 6 5 4 3 2 1 0 S...

Page 37: ...following sources External reset pin during power on or if user configured via UCFG1 Power on detect Brownout detect Watchdog timer Software reset UART break character detect reset For every reset so...

Page 38: ...a Power on reset If RST is still asserted after the Power on reset is over R_EX will be set 1 R_SF software reset Flag Cleared by software by writing a logic 0 to the bit or a Power on reset 2 R_WD W...

Page 39: ...er or Counter function is selected by control bits TnC T x 0 and 1 for Timers 0 and 1 respectively in the Special Function Register TMOD Timer 0 and Timer 1 have five operating modes modes 0 1 2 3 and...

Page 40: ...xcept that all 16 bits of the timer register THn and TLn are used See Figure 16 Table 26 Timer Counter Auxiliary Mode register TAMOD address 8Fh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol T1M2 T0M2 Res...

Page 41: ...still be used by the serial port as a baud rate generator or in any application not requiring an interrupt 7 5 Mode 6 In this mode the corresponding timer can be changed to a PWM with a full period of...

Page 42: ...ter 1 on off 7 TF1 Timer 1 overflow flag Set by hardware on Timer Counter overflow Cleared by hardware when the interrupt is processed or by software except in mode 6 see above when it is cleared in h...

Page 43: ...nction the C T bit must be cleared selecting PCLK as the clock source for the timer 8 Real time clock system timer The P89LPC9321 has a simple Real time Clock System Timer that allows a user to contin...

Page 44: ...gic 1 the counter is first loaded with RTCH RTCL 1111111 and will count down When it reaches all 0 s the counter will be reloaded again with RTCH RTCL 1111111 and a flag RTCF RTCCON 7 will be set The...

Page 45: ...so be a source to wake up the device 8 3 1 Real time clock read back Users can read RTCDATH and RTCDATL registers and get the 16 bit counter portion of the RTC 8 4 Reset sources affecting the Real tim...

Page 46: ...cillator 100 0 00 High frequency crystal Watchdog oscillator DIVM 01 Medium frequency crystal 10 Low frequency crystal 11 Watchdog oscillator DIVM 1 00 High frequency crystal Internal RC oscillator 01...

Page 47: ...to help divide PCLK into a frequency between 0 5 MHz and 1 MHz 9 2 CCU Clock prescaling This CCUCLK can further be divided down by a prescaler The prescaler is implemented as a 10 bit free running cou...

Page 48: ...of TOR2H TOR2L Down counting When the timer contents are 0000H the next CCUCLK cycle will set the counter value to the contents of TOR2H TOR2L During the CCUCLK cycle when the reload is performed the...

Page 49: ...r downcounting to TH2 When TL2 is written FFh TH2 for upcounting and 00h for downcounting will be loaded to CCU Timer The user will not need to rewrite TH2 again for an 8 bit timer operation unless th...

Page 50: ...are match occurs Enabled compare actions take place even if the interrupt is disabled 5 TPCR2L 5 Prescaler bit 5 6 TPCR2L 6 Prescaler bit 6 7 TPCR2L 7 Prescaler bit 7 Table 36 CCU prescaler control re...

Page 51: ...the values to be latched immediately and the value of TCOU2 will always read as zero In PWM mode writing a one to TCOU2 will cause the contents of the shadow registers to be updated on the next CCU T...

Page 52: ...ored to the corresponding interrupt The interrupt flag must be cleared manually by writing a logic 0 to it When reading the input capture register ICRxL must be read first When ICRxL is read the conte...

Page 53: ...fter the change from TOR to TOR 1 When the timer changes direction at the bottom in this example it counts 0001H 0000H 0001H The CCU Timer overflow interrupt flag is set in the counter CCUCLK cycle af...

Page 54: ...n will immediately stop all activity on the PWM pins and set them to a predetermined state defined by FCOx bit In PWM Mode the FCOx bits in the CCCRx register hold the value the pin is forced to durin...

Page 55: ...y can be in the range of PCLK to PCLK 16 Setting the PLLEN bit in TCR20 starts the PLL When PLLEN is set it will not read back a one until the PLL is in lock At this time the PWM unit is ready to oper...

Page 56: ...nd interrupts can occur simultaneously in system usage To resolve this situation a priority encode function of the seven interrupt bits in TIFR2 SFR is implemented after each bit is AND ed with the co...

Page 57: ...x x 0 0 0 Table 46 CCU interrupt status encode register TISE2 address DEh bit description Bit Symbol Description 2 0 ENCINT 2 0 CCU Interrupt Encode output When multiple interrupts happen more than on...

Page 58: ...If EA bit in IEN0 ECCU bit in IEN1 and TOCIE2C bit are all set the program counter will vectored to the corresponding interrupt Cleared by software 6 TOCF2D Output Compare Channel D Interrupt Flag Bit...

Page 59: ...nction Register SCON The baud rate is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator see Section 10 6 Baud Rate generator and selection 10 3 Mode 2 11 bits are tran...

Page 60: ...the BRGR1 and BRGR0 SFRs The UART can use either Timer 1 or the baud rate generator output as determined by BRGCON 2 1 see Figure 26 Note that Timer T1 is further divided by 2 if the SMOD1 bit PCON 7...

Page 61: ...state until a stop bit has been received The break detect can be used to reset the device and force the device into ISP mode by setting the EBRR bit AUXR1 6 1 0 0 X CCLK 32 1 X CCLK 16 1 1 0 0 CCLK 25...

Page 62: ...ed in Modes 2 and 3 Set or clear by software as desired 4 REN Enables serial reception Set by software to enable reception Clear by software to disable reception 5 SM2 Enables the multiprocessor commu...

Page 63: ...id STOP bit at the end of the frame Cleared by software 4 DBISEL Double buffering transmit interrupt select Used only if double buffering is enabled This bit controls the number of interrupts that can...

Page 64: ...ooking for another 1 to 0 transition This provides rejection of false start bits If the start bit proves valid it is shifted into the input shift register and reception of the rest of the frame will p...

Page 65: ...th data bit goes into RB8 and the first 8 data bits go into SBUF 10 13 Framing error and RI in Modes 2 and 3 with SM2 1 If SM2 1 in modes 2 and 3 RI and FE behaves as in the following table Fig 28 Ser...

Page 66: ...be disabled If disabled DBMOD i e SSTAT 7 0 the UART is compatible with the conventional 80C51 UART If enabled the UART allows writing to SnBUF while the previous data is being shifted out 10 16 Doub...

Page 67: ...Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter If INTLO is logic 1 the new data will be loaded and a Tx interrupt will occur at the end of the STOP bit o...

Page 68: ...ill occur at the end of the STOP bit of the data currently in the shifter 9 Go to 4 10 Note that if DBISEL is logic 1 and the CPU is writing to SBUF when the STOP bit of the last data is shifted out t...

Page 69: ...p to show the versatility of this scheme In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves Slave 0 requires a 0 in bit 0 and it ignores bit 1 Sl...

Page 70: ...stic purposes A typical I2C bus configuration is shown in Figure 31 Depending on the state of the direction bit R W two types of data transfers are possible on the I2C bus Data transfer from a master...

Page 71: ...is located at the MSB of I2DAT 11 2 I2C slave address register I2ADR register is readable and writable and is only used when the I2C interface is set to slave mode In master mode this register has no...

Page 72: ...ition in master mode or recovering from an error condition in slave mode If the STA and STO are both set then a STOP condition is transmitted to the I2C bus if it is in master mode and transmits a STA...

Page 73: ...dition is transmitted to the I2C bus When the bus detects the STOP condition it will clear STO bit automatically In slave mode setting this bit can recover from an error condition In this case no STOP...

Page 74: ...set to 1 to enable the I2C function If the AA bit is 0 it will not acknowledge its own slave address or the general call address in the event of another device becoming master of the bus and it can no...

Page 75: ...bit has been received the SI bit is set again and the possible status codes are 18h 20h or 38h for the master mode or 68h 78h or 0B0h if the slave mode was enabled setting AA Logic 1 The appropriate a...

Page 76: ...data direction bit which is 0 W If the direction bit is 1 R it will enter Slave Transmitter Mode After the address and the direction bit have been received the SI bit is set and a valid status code c...

Page 77: ...ested When the microcontrollers wishes to become the bus master the hardware waits until the bus is free before the master mode is entered so that a possible slave action is not interrupted If bus arb...

Page 78: ...BUS 002aaa899 ADDRESS REGISTER COMPARATOR SHIFT REGISTER 8 I2ADR ACK BIT COUNTER ARBITRATION SYNC LOGIC 8 I2DAT TIMING AND CONTROL LOGIC SERIAL CLOCK GENERATOR CCLK interrupt INPUT FILTER OUTPUT STAG...

Page 79: ...T action or 0 1 0 x STOP condition will be transmitted STO flag will be reset no I2DAT action 1 1 0 x STOP condition followed by a START condition will be transmitted STO flag will be reset 20h SLA W...

Page 80: ...eiver mode Status code I2STAT Status of the I2C hardware Application software response Next action taken by I2C hardware to from I2DAT to I2CON STA STO SI STA 08H A START condition has been transmitte...

Page 81: ...TA STO SI AA 60H Own SLA W has been received ACK has been received no I2DAT action or x 0 0 0 Data byte will be received and NOT ACK will be returned no I2DAT action x 0 0 1 Data byte will be received...

Page 82: ...has been received ACK has been returned Read data byte or x 0 0 0 Data byte will be received and NOT ACK will be returned read data byte x 0 0 1 Data byte will be received and ACK will be returned 98H...

Page 83: ...omes free Table 75 Slave Receiver mode continued Status code I2STAT Status of the I2C hardware Application software response Next action taken by I2C hardware to from I2DAT to I2CON STA STO SI AA Tabl...

Page 84: ...ll be transmitted when the bus becomes free no I2DAT action 1 0 0 1 Switched to not addressed SLA mode Own slave address will be recognized General call address will be recognized if I2ADR 0 1 A START...

Page 85: ...abled i e SPEN SPCTL 6 0 reset value If the SPI is configured as a master i e MSTR SPCTL 4 1 and P2 4 is configured as an output via the P2M1 4 and P2M2 4 SFR bits If the SS pin is ignored i e SSIG SP...

Page 86: ...e data word is transmitted first 0 The MSB of the data word is transmitted first 6 SPEN SPI Enable 1 The SPI is enabled 0 The SPI is disabled and all SPI pins will be port pins 7 SSIG SS IGnore 1 MSTR...

Page 87: ...figured in quasi bidirectional mode When a device initiates a transfer it can configure P2 4 as an output and drive it low forcing a mode change in the other device see Section 12 4 Mode change on SS...

Page 88: ...BIT SHIFT REGISTER SPI CLOCK GENERATOR 8 BIT SHIFT REGISTER MISO MOSI SPICLK port port MISO MOSI SPICLK SS slave 8 BIT SHIFT REGISTER MISO MOSI SPICLK SS Table 82 SPI master and slave selection SPEN S...

Page 89: ...ow Data written to the SPDAT register of the master is shifted out of the MOSI pin of the master to the MOSI pin of the slave at the same time the data in SPDAT register in slave side is shifted out o...

Page 90: ...t to indicate data collision when the data register is written during transmission In this case the data currently being transmitted will continue to be transmitted but the new data i e the one causin...

Page 91: ...UM10310 P89LPC9321 User manual 1 Not defined Fig 42 SPI slave transfer format with CPHA 0 1 2 3 4 5 6 7 8 MSB LSB DORD 0 DORD 1 6 1 5 2 4 3 3 4 2 5 1 6 LSB MSB MSB LSB DORD 0 DORD 1 6 1 5 2 4 3 3 4 2...

Page 92: ...UM10310 P89LPC9321 User manual 1 Not defined Fig 43 SPI slave transfer format with CPHA 1 1 2 3 4 5 6 7 8 MSB LSB DORD 0 DORD 1 6 1 5 2 4 3 3 4 2 5 1 6 LSB MSB MSB LSB DORD 0 DORD 1 6 1 5 2 4 3 3 4 2...

Page 93: ...UM10310 P89LPC9321 User manual 1 Not defined Fig 44 SPI master transfer format with CPHA 0 1 2 3 4 5 6 7 8 MSB LSB 6 1 5 2 4 3 3 4 2 5 1 6 LSB MSB MSB LSB DORD 0 DORD 1 6 1 5 2 4 3 3 4 2 5 1 6 LSB MS...

Page 94: ...n or an internal reference voltage Otherwise the output is a zero Each comparator may be configured to cause an interrupt when the output value changes The comparators inputs can be amplified by using...

Page 95: ...0 Table 84 Comparator Control register CMP1 address ACh CMP2 address ADh bit description Bit Symbol Description 0 CMFn Comparator interrupt flag This bit is set by hardware whenever the comparator out...

Page 96: ...The two comparators use one common interrupt vector The interrupt will be generated when the interrupt enable bit EC in the IEN1 register is set and the interrupt system is enabled via the EA bit in...

Page 97: ...wer consumption is an issue To minimize power consumption the user can power down the comparators by disabling the comparators and setting PCONA 5 to logic 1 or simply putting the device in Total Powe...

Page 98: ...16 by configuring PGAG11 and PGAG10 bits PGA is enabled by setting ENPGA1 bit If ENPGA1 is cleared PGA1 is disabled and bypassed which means the PGA1 gain value is 1 Four external input signals are s...

Page 99: ...0 Symbol ENPGA1 PGASEL11 PGASEL10 PGATRIM1 PGAG11 PGAG10 Reset 0 0 0 0 0 0 0 0 Table 87 PGA1 Control register PGACON1 address FFE1h bit description Bit Symbol Description 1 0 PGAG11 PGAG10 PGA Gain se...

Page 100: ...then any key connected to Port0 which is enabled by KBMASK register is will cause the hardware to set KBIF 1 and generate an interrupt if it has been enabled The interrupt may be used to wake up the C...

Page 101: ...sequence see Section 15 2 Additional bits in WDCON allow the user to select the clock source for the WDT and the prescaler When the timer is not enabled to reset the device on underflow the WDT can b...

Page 102: ...ues in the WDCON and WDL SFRs are loaded to the control register and the 8 bit down counter Before the feed sequence any new values written to these two SFRs will not take effect To avoid a watchdog r...

Page 103: ...may be removed In watchdog mode WDTE 1 writing the WDCON register must be IMMEDIATELY followed by a feed sequence to load the WDL to the 8 bit down counter and the WDCON to the shadow register If wri...

Page 104: ...ows In watchdog mode a feed sequence will clear this bit It can also be cleared by writing a logic 0 to this bit in software 2 WDRUN Watchdog Run Control The watchdog timer is started when WDRUN 1 and...

Page 105: ...ation logic it can take two old clock cycles before the old clock source is deselected and then an additional two new clock cycles before the new clock source is selected Since the prescaler starts co...

Page 106: ...cause an interrupt WDTOF is cleared by writing a logic 0 to this bit in software When an underflow occurs the contents of WDL is reloaded into the down counter and the watchdog timer immediately begi...

Page 107: ...a periodic wake up is determined by the power consumption of the internal oscillator source used to produce the wake up The Real time clock running from the internal RC oscillator can be used The pow...

Page 108: ...r manipulates the DPH and DPL registers the upper and lower bytes of the current DPTR will be affected by the setting of DPS The MOVX instructions have limited application for the P89LPC9321 since the...

Page 109: ...egister and the address is in the DEEADR register Each write requires approximately 4 ms to complete Each read requires three machines after writing the address to the DEEADR register Table 103 Data E...

Page 110: ...ftware write 17 1 Data EEPROM read A byte can be read via polling or interrupt 1 Write to DEECON with ECTL1 ECTL0 DEECON 5 4 00 and correct bit 8 address to EADR8 Note that if the correct values are a...

Page 111: ...AT register will be initialized If a write to the DEEDAT register occurs followed by a hardware reset a write to the DEEADR register without a prior write to the DEEDAT register will result in a read...

Page 112: ...EIF DEECON 7 bit until it is set to logic 1 If EIEE or EA is logic 0 the interrupt is disabled and only polling is enabled When EEIF is logic 1 the operation is complete 6 Poll EWERR0 flag If EWERR0 D...

Page 113: ...mers IAP Lite allows individual and multiple bytes of code memory to be used for data storage and programmed under control of the end application Internal fixed boot ROM containing low level In Applic...

Page 114: ...code memory will not be affected Writing the erase program command 68H to FMCON will start the erase program process and place the CPU in a program idle state The CPU will remain in this idle state u...

Page 115: ...byte R7 pointer to data buffer in RAM byte Outputs R7 status byte Table 105 Flash Memory Control register FMCON address E4h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol R HVA HVE SV OI Symbol W FMCMD 7...

Page 116: ...eturn MOV A R7 read status ANL A 0FH save only four lower bits JNZ BAD CLR C clear error flag if good RET and return BAD SETB C set error flag RET and return A C language routine to load the page regi...

Page 117: ...ed from the factory the upper 512 bytes of user code space contains a serial In System Programming ISP loader allowing for the device to be programmed in circuit through the serial port This ISP boot...

Page 118: ...t can be manually forced into ISP operation If the factory default setting for the Boot Vector is changed it will no longer point to the factory pre programmed ISP boot loader code If this happens the...

Page 119: ...ist of ASCII characters used to represent hexadecimal values and are summarized below NNAAAARRDD DDCC crlf In the Intel Hex record the NN represents the number of data bytes in the record The P89LPC93...

Page 120: ...06070809DC3 01 Read Version Id 00xxxx01cc Where xxxx required field but value is a don t care cc checksum Example 00000001FF 02 Miscellaneous Write Functions 02xxxx02ssddcc Where xxxx required field b...

Page 121: ...1 0A Security Byte 2 0B Security Byte 3 0C Security Byte 4 0D Security Byte 5 0E Security Byte 6 0F Security Byte 7 10 Manufacturer Id 11 Device Id 12 Derivative Id Example 0100000312EA 04 Erase Secto...

Page 122: ...gm_mtp void 0xFF00 set pointer to IAP entry point key 0x96 set the authorization key pgm_mtp execute the IAP function call After the function call is processed by the IAP routine the authorization key...

Page 123: ...e Configuration Write Protect bit CWP is a logic 0 writes to the configuration bytes are enabled The CWP bit is set by programming the BOOTSTAT register This bit is cleared by using the Clear Configur...

Page 124: ...settings Cycle is aborted Memory contents are unchanged CRC output is invalid 2 HVE High Voltage Error Set if error detected in high voltage generation circuits Cycle is aborted Memory contents may b...

Page 125: ...F1 0h use IDATA Return parameter s R7 status Carry set on error clear on no error Read Version Id Input parameters ACC 01h Return parameter s R7 IAP version id Misc Write requires key Input parameter...

Page 126: ...ity Byte 1 0A Security Byte 2 0B Security Byte 3 0C Security Byte 4 0D Security Byte 5 0E Security Byte 6 0F Security Byte 7 Return parameter s R7 register data if no error else error status Carry set...

Page 127: ...put parameters ACC 06h Return parameter s R4 CRC bits 31 24 R5 CRC bits 23 16 R6 CRC bits 15 8 R7 CRC bits 7 0 if no error R7 error status if error Carry set on error clear on no error Read User Code...

Page 128: ...When set 1 enables the watchdog timer reset When cleared 0 disables the watchdog timer reset The timer may still be used to generate an interrupt Refer to Table 96 Watchdog timer configuration for det...

Page 129: ...ts EDISx SPEDISx MOVCDISx Effects on Programming 0 0 0 None 0 0 1 Security violation flag set for sector CRC calculation for the specific sector Security violation flag set for global CRC calculation...

Page 130: ...ble CWE commands 6 CWP Configuration Write Protect bit Protects inadvertent writes to the user programmable configuration bytes UCFG1 BOOTVEC and BOOTSTAT If programmed to a logic 1 the writes to thes...

Page 131: ...1 1 96 to 97 SUBB A data Subtract immediate from A with borrow 2 1 94 INC A Increment A 1 1 04 INC Rn Increment register 1 1 08 to 0F INC dir Increment direct byte 2 1 05 INC Ri Increment indirect mem...

Page 132: ...Rn data Move immediate to register 2 1 78 to 7F MOV dir A Move A to direct byte 2 1 F5 MOV dir Rn Move register to direct byte 2 2 88 to 8F MOV dir dir Move direct byte to direct byte 3 2 85 MOV dir R...

Page 133: ...12 RET Return from subroutine 1 2 22 RETI Return from interrupt 1 2 32 AJMP addr 11 Absolute jump unconditional 2 2 016E1 LJMP addr 16 Long jump unconditional 3 2 02 SJMP rel Short jump relative addr...

Page 134: ...luding without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof Suitabil...

Page 135: ...high byte TPCR2H address CBh bit allocation 49 Table 34 CCU prescaler control register high byte TPCR2H address CBh bit description 49 Table 35 CCU prescaler control register low byte TPCR2L address C...

Page 136: ...cation 100 Table 93 Keypad Control register KBCON address 94h bit description 100 Table 94 Keypad Interrupt Mask register KBMASK address 86h bit allocation 101 Table 95 Keypad Interrupt Mask register...

Page 137: ...te generation for UART Modes 1 3 61 Fig 27 Serial Port Mode 0 double buffering must be disabled 64 Fig 28 Serial Port Mode 1 only single transmit buffering case is shown 65 Fig 29 Serial Port Mode 2 o...

Page 138: ...clock source 44 8 2 Changing RTCS1 RTCS0 45 8 3 Real time clock interrupt wake up 45 8 3 1 Real time clock read back 45 8 4 Reset sources affecting the Real time clock 45 9 Capture Compare Unit CCU 4...

Page 139: ...dditional features 107 16 1 Software reset 108 16 2 Dual Data Pointers 108 17 Data EEPROM 109 17 1 Data EEPROM read 110 17 2 Data EEPROM write 110 17 3 Hardware reset 111 17 4 Multiple writes to the D...

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