P5040/P5020 Reference Design Board User Guide, Rev. 0
58
Freescale Semiconductor
Programming Model
7.1.11
Address Register (PX_ADDR)
The address register is a general-purpose R/W register used to index an internal 256-byte SRAM array.
PX_ADDR resets at initial Power-ON or via chassis reset sources. The register preserves its value between
COP- or watchdog-initiated resets. PX_ADDR write is non-atomic.
Figure 32. SRAM Address Register (PX_ADDR)
Exercise caution when sharing SRAM between processors and/or the ngPIXIS GMSA core.
7.1.12
Board Configuration Register (PX_BRDCFG2)
This register controls board configurations; they can be changed at any time.
Figure 33. Board Configuration Register 2 (PX_BRDCFG2)
Table 39. MII-1 Bus Selection
EMI1_SEL1
EMI1_SEL0
Connected PHYs
0
0
Onboard Vitesse
RGMII PHY
0
1
Onboard SGMII PHY
1
0
Reserved
1
1
Reserved
0
1
2
3
4
5
6
7
R
ADDR
W
Reset
0
0
0
0
0
0
0
0
Offset
0x0A
Table 40. PX_ADDR Field Descriptions
Bits
Name
Description
0–7
ADDR
PX_DATA read/writes to this SRAM address array.
0
1
2
3
4
5
6
7
R
MGN_DISABLE
GPIO_TEST
REG/GPIO
SEL
THERM_SHTN_ON
PS_PL_CNTR
_SEL
PS_CA_CNTR
_SEL
LANE_SATA_
SEL
—
W
Reset
1
0
0
0
1
1
—
1
1
The Default depends on chip: For P5040 = ‘1’, otherwise ‘0’.
0
Offset
0x0B