P4080 Development System User’s Guide, Rev. 0
Freescale Semiconductor
43
Configuration
delay has completed. If no character is received, the OCM mode falls back to memory configuration mode.
Otherwise, while the system is still prevented from powering up, commands are accepted over the serial
port, allowing SW/EN registers to be edited in memory. When the user has completed any configuration
commands, the “GO” command allows the normal power-up sequence to proceed.
6.1.2
Configuration Switches
The SW registers are formatted as shown in this table.
Switch names exactly match the name on the schematics and on the printed-circuit board in most cases,
except where a spare has been newly assigned and only an FPGA has changed. See the P4080DS
Configuration Sheet, which helps configure the system to a default configuation and has more detail as to
the functionality of the these switches. It is also the most up-to-date document for any addition or change
in features before
,” is updated. This table summarizes the switches.
Table 20. Configuration Switches Format
DIP Switch Label
1
2
3
4
5
6
7
8
ngPIXIS Register Bit
(Power Arch. “big endian” format)
0
1
2
3
4
5
6
7
Table 21. Configuration Switches
Group
Switches
Configuration Signals
Class
SW1
(1–5)
cfg_rcw_src[0:4]
Dynamic
(6)
cfg_dram_type
(7)
cfg_rsp_dis
(8)
cfg_elbc_ecc
SW2
1
cfg_eng_use[0]
Dynamic
2
cfg_eng_use[1]
3
cfg_eng_use[2]
4
cfg_eng_use[3]
5
cfg_eng_use[4]
6
cfg_eng_use[5]
7
cfg_eng_use[6]
8
cfg_eng_use[7]
SW3
1
sd1_refspread
Static
2
sd1_refclksel
3
sd2_refclksel
4
sd3_refclksel
5
n/a
—
(6–8)
sysclk[0:2]
Static