NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 865 / 1761

QuadSPI_FR field descriptions (continued)
Field Description
17
RBOF
RX Buffer Overflow Flag. Set when not all the data read from the serial flash device could be pushed into
the RX Buffer.
The IP Command leading to this condition is continued until the number of bytes according to the
QSPI_IPCR[IDATSZ] field has been read from the serial flash device.
The content of the RX Buffer is not changed.
16
RBDF
RX Buffer Drain Flag. Will be set if the QuadSPI_SR[RXWE] status bit is asserted.
Writing 1 into this bit triggers one of the following actions:
• If the RX Buffer has up to QuadSPI_RBCT[WMRK] valid entries then the flag is cleared.
• If the RX Buffer has more than QuadSPI_RBCT[WMRK] valid entries and the
QuadSPI_RSER[RBDDE] bit is not set (flag driven mode) a RX Buffer POP event is triggered.
The flag remains set if the RX Buffer contains more than QuadSPI_RBCT[WMRK] valid entries after the
RX Buffer POP event is finished.
The flag is cleared if the RX Buffer contains less than or equal to QuadSPI_RBCT[WMRK] valid entries
after the RX Buffer POP event is finished.
Refer to "Receive Buffer Drain Interrupt or DMA Request" section in Normal Mode Interrupt and DMA
Requests , for details.
15
ABSEF
AHB Sequence Error Flag. Set when the execution of an AHB Command is started with a WRITE or
WRITE_DDR Command in the sequence pointed to by the QSPI_BUFxCR register. (QSPI_BUFxCR
implies any one of QSPI_BUF0CR/QSPI_BUF1CR/QSPI_BUF2CR/QSPI_BUF3CR.)
Communication with the serial flash device is terminated before the execution of WRITE/WRITE_DDR
command by the QuadSPI module.
The AHB bus request which triggered this command is answered with an ERROR response.
14
AITEF
AHB Illegal transaction error flag. Set whenever there is no response generated from QSPI to AHB bus in
case of illegal transaction and the watchdog timer expires.The timer value is taken as parameter.
13
AIBSEF
AHB Illegal Burst Size Error Flag. Set whenever the total burst size (size x beat) of an AHB transaction is
greater than the prefetch data size. The prefecth data size is defined by QSPI_BUFxCR[ADATSZ] or data
size mentioned in the sequence pointed to by the SEQID field in case ADATSZ = 0. Refer to
HBURST
Support for more details on HBURST feature.
12
ABOF
AHB Buffer Overflow Flag. Set when the size of the AHB access exceeds the size of the AHB buffer. This
condition can occur only if the QSPI_BUFxCR[ADATSZ] field is programmed incorrectly.
The AHB Command leading to this condition is continued until the number of entries according to the
QSPI_BUFxCR[ADATSZ] field has been read from the serial flash device.
The content of the AHB Buffer is not changed.
11
Reserved
This field is reserved.
10–8
Reserved
This field is reserved.
7
IPAEF
IP Command Trigger during AHB Access Error Flag. Set when the following condition occurs:
• A write access occurs to the QSPI_IPCR[SEQID] field and the QSPI_SR[AHB_ACC] bit is set. Any
command leading to the assertion of the IPAEF flag is ignored.
6
IPIEF
IP Command Trigger could not be executed Error Flag. Set when the QSPI_SR[IP_ACC] bit is set (i.e. an
IP triggered command is currently executing) and any of the following conditions occurs:
• Write access to the QSPI_IPCR register. Any command leading to the assertion of the IPIEF flag is
ignored
• Write access to the QSPI_SFAR register.
• Write access to the QSPI_RBCT register.
Table continues on the next page...
Chapter 33 Quad Serial Peripheral Interface (QuadSPI)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 865