NXP Semiconductors MWCT101 S Series, Reference Manual

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Table 33-3. QuadSPI_SOCCR[SOCCFG] bit field
description
Bit field name Bit field description
010 : DIV by 3
011 : DIV by 4
100 : DIV by 5
101: DIV by 6
110: DIV by 7
111: DIV by 8
33.2 Introduction
The Quad Serial Peripheral Interface (QuadSPI) block acts as an interface to a single or
two external serial flash devices, each with up to eight bidirectional data lines.
33.2.1 Features
The QuadSPI supports the following features:
• Flexible sequence engine to support various flash vendor devices. As there is no
specific standard, the module supports various kind of flashes from different vendors.
Refer
Serial Flash Devices for example sequences.
• Single, dual, quad and octal modes of operation.
• Double data rate (DDR)/Double trasfer rate (DTR) mode wherein the data is
generated on every edge of the serial flash clock.
• Support for flash data strobe signal for data sampling in DDR and Single data rate
(SDR) mode.
• Support for HyperRAM.
• AHB master to read RX Buffer data via AMBA AHB bus (64-bit width interface) or
IP registers space (32-bit access) and fill TX Buffer via IPS register space (32-bit
access).
• AHB master can be a DMA with configurable inner loop size.
• Multimaster accesses with priority
• Flexible and configurable buffer for each master
Chapter 33 Quad Serial Peripheral Interface (QuadSPI)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 825