NXP Semiconductors MWCT101 S Series, Reference Manual

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• The software configuration options provided for QuadSPI through registers
SOC_CONFIG and SCLK_CONFIG should be done before enabling clock of
QuadSPI.
• Configure the QuadSPI module before configuring the ALT mode selection for
selecting QuadSPI pads.
NOTE
• User should ensure that communication is complete on
QuadSPI before low power mode entry is initiated.
• Divider values of programmable divider (see QuadSPI
clocking diagram in Module clocks for details) should be
programmed before enabling it. The divider is enabled by
default.
33.1.8 Recommended programming sequence
Following is the recommended programming sequence:
1. Enable PCC_QSPI[CGC]
2. Program QuadSPI_MCR[SCLKCFG] and QuadSPI_SOCCR[SOCCFG]
3. Program QuadSPI_MCR[MDIS] to 0
33.1.9 Clock ratio between QuadSPI clocks
Below clock relationship should be maintained between SFIF_CLK (flash internal
reference clock ) and AHB read interface clock (bus clock) of QuadSPI :
• SFIF_CLK ≤ AHB read interface clock
33.1.10 QuadSPI_MCR[SCLKCFG] implementation
Table 33-2. QuadSPI_MCR[SCLKCFG] bit field description
Bit field name Bit field description
SCLKCFG[7] Enables input buffer of QSPI pads for SDR and HyperRAM modes
0: ibe of all QSPI pads disabled
1: ibe of all QSPI pads enabled
SCLKCFG[6]
Quadspi Clocking mode selection. Always program SCLKCFG[6] twice while configuring mode
selection.
0: Selecting SYS_CLK as AHB read interface Clock and module clock. Mandatory for HSRUN
80/RUN 64/RUN 80 configurations.
Table continues on the next page...
Chip-specific QuadSPI information
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
822 NXP Semiconductors