NXP Semiconductors MWCT101 S Series, Reference Manual

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SCG_VCCR field descriptions (continued)
Field Description
1010 Divide-by-11
1011 Divide-by-12
1100 Divide-by-13
1101 Divide-by-14
1110 Divide-by-15
1111 Divide-by-16
DIVSLOW Slow Clock Divide Ratio
0000 Divide-by-1
0001 Divide-by-2
0010 Divide-by-3
0011 Divide-by-4
0100 Divide-by-5
0101 Divide-by-6
0110 Divide-by-7
0111 Divide-by-8
1000 Reserved
1001 Reserved
1010 Reserved
1011 Reserved
1100 Reserved
1101 Reserved
1110 Reserved
1111 Reserved
26.3.6 HSRUN Clock Control Register (SCG_HCCR)
This register controls the system clock source and the system clock dividers for the core,
platform, external and bus clock domains when in HSRUN mode only. This register can
only be written using a 32-bit write. Selecting a different clock source when in HSRUN
requires that clock source to be enabled first and be valid before system clocks switch to
that clock source. If system clock divide ratios also change when selecting a different
clock mode when in HSRUN, new system clock divide ratios will not take affect until
new clock source is valid.
Address: 4006_4000h base + 1Ch offset = 4006_401Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
SCS
0
DIVCORE Reserved
0
DIVBUS DIVSLOW
W
Reset
0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Chapter 26 System Clock Generator (SCG)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 541