NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 463 / 1761

Field Function
—
15-8
WINHIGH
High byte of Watchdog Window
7-0
WINLOW
Low byte of Watchdog Window
21.4 Functional description
The WDOG module provides a fail safe mechanism to ensure the system can be reset to a
known state of operation in case of system failure, such as the CPU clock stopping or
there being a run away condition in the software code. The watchdog counter runs
continuously off a selectable clock source and expects to be serviced (refreshed)
periodically. If it is not, it generates a reset triggering event.
21.4.1 Clock source
The watchdog counter has the following clock source options selected by programming
CS[CLK]:
• bus clock
• Low-Power Oscillator clock (LPO_CLK)
• internal clock
• external clock
The options allow software to select a clock source independent of the bus clock for
applications that need to meet more robust safety requirements. Using a clock source
other than the bus clock ensures that the watchdog counter continues to run if the bus
clock is somehow halted; see
Backup reset .
NOTE
The default clock source of WDOG should be enabled after its
funcitonal reset is deasserted, for the WDOG module to
function properly.
An optional fixed prescaler for all clock sources allows for longer timeout periods. When
CS[PRES] is set, the clock source is prescaled by 256 before clocking the watchdog
counter.
Chapter 21 Watchdog timer (WDOG)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 463