NXP Semiconductors MWCT101 S Series, Reference Manual

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Field Function
22-21
M3SM
Bus Master 3 Supervisor Mode Access Control
Defines the access controls for bus master 3 in Supervisor mode.
00b - r/w/x; read, write and execute allowed
01b - r/x; read and execute allowed, but no write
10b - r/w; read and write allowed, but no execute
11b - Same as User mode defined in M3UM
20-18
M3UM
Bus Master 3 User Mode Access Control
Defines the access controls for bus master 3 in User mode. M3UM consists of three independent bits,
enabling read (r), write (w), and execute (x) permissions. In M3UM[2:0]: M3UM[2] controls read
permissions, M3UM[1] controls write permissions, and M3UM[0] controls execute permissions. For each
bit:
0b - An attempted access of that mode may be terminated with an access error (if not allowed by
another descriptor) and the access not performed
1b - Allows the given access type to occur
17
—
Reserved
This bit must be written with a zero.
16-15
M2SM
Bus Master 2 Supervisor Mode Access Control
Defines the access controls for bus master 2 in Supervisor mode.
00b - r/w/x; read, write and execute allowed
01b - r/x; read and execute allowed, but no write
10b - r/w; read and write allowed, but no execute
11b - Same as User mode defined in M2UM
14-12
M2UM
Bus Master 2 User Mode Access Control
Defines the access controls for bus master 2 in User mode. M2UM consists of three independent bits,
enabling read (r), write (w), and execute (x) permissions. In M2UM[2:0]: M2UM[2] controls read
permissions, M2UM[1] controls write permissions, and M2UM[0] controls execute permissions. For each
bit:
0b - An attempted access of that mode may be terminated with an access error (if not allowed by
another descriptor) and the access not performed
1b - Allows the given access type to occur
11
M1PE
Bus Master 1 Process Identifier Enable
NOTE: For RGDAAC0: Only bus master 1 can write to M1PE.
0b - Do not include the process identifier in the evaluation
1b - Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
10-9
M1SM
Bus Master 1 Supervisor Mode Access Control
Defines the access controls for bus master 1 in Supervisor mode.
NOTE: For RGDAAC0: Only bus master 1 can write to M1SM.
00b - r/w/x; read, write and execute allowed
01b - r/x; read and execute allowed, but no write
10b - r/w; read and write allowed, but no execute
11b - Same as User mode defined in M1UM
8-6
M1UM
Bus Master 1 User Mode Access Control
Defines the access controls for bus master 1 in User mode. M1UM consists of three independent bits,
enabling read (r), write (w), and execute (x) permissions. In M1UM[2:0]: M1UM[2] controls read
permissions, M1UM[1] controls write permissions, and M1UM[0] controls execute permissions.
NOTE: For RGDAAC0: Only bus master 1 can write to M1UM.
For each bit:
0b - An attempted access of that mode may be terminated with an access error (if not allowed by
another descriptor) and the access not performed
Table continues on the next page...
Chapter 13 Memory Protection Unit (MPU)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 227