NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 218 / 1761

Field Function
M0SM Defines the access controls for bus master 0 in Supervisor mode.
00b - r/w/x; read, write and execute allowed
01b - r/x; read and execute allowed, but no write
10b - r/w; read and write allowed, but no execute
11b - Same as User mode defined in M0UM
2-0
M0UM
Bus Master 0 User Mode Access Control
Defines the access controls for bus master 0 in User mode. M0UM consists of three independent bits,
enabling read (r), write (w), and execute (x) permissions. In M0UM[2:0]: M0UM[2] controls read
permissions, M0UM[1] controls write permissions, and M0UM[0] controls execute permissions. For each
bit:
0b - An attempted access of that mode may be terminated with an access error (if not allowed by
another descriptor) and the access not performed
1b - Allows the given access type to occur
13.4.8 Region Descriptor 0, Word 3 (RGD0_WORD3)
13.4.8.1 Offset
Register Offset
RGD0_WORD3 40Ch
13.4.8.2 Function
The fourth word of the region descriptor contains the optional process identifier and
mask, plus the region descriptor’s valid bit.
13.4.8.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
PID PIDMASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
VLD
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
MPU register descriptions
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
218 NXP Semiconductors