NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 211 / 1761

13.4.3.4 Fields
Field Function
31-0
EADDR
Error Address
Indicates the reference address from slave port n that generated the access error
13.4.4 Error Detail Register, slave port n (EDR0 - EDR4)
13.4.4.1 Offset
Register Offset
EDR0 14h
EDR1 1Ch
EDR2 24h
EDR3 2Ch
EDR4 34h
13.4.4.2 Function
When the MPU detects an access error on slave port n, 32 bits of error detail are captured
in this read-only register and the corresponding bit in CESR[SPERRn] is set. Information
on the faulting address is captured in the corresponding EARn register at the same time.
This register and the corresponding EARn register contain the most recent access error;
there are no hardware interlocks with CESR[SPERRn] as the error registers are always
loaded upon the occurrence of each protection violation.
Chapter 13 Memory Protection Unit (MPU)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 211