NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 201 / 1761

Chapter 13
Memory Protection Unit (MPU)
13.1 Chip-specific MPU information
On this device, NXP's system MPU implements the safety mechanisms to prevent
masters from accessing restricted memory regions. This system MPU provides memory
protection at the level of the Crossbar Switch. Each Crossbar master (Core, DMA) can be
assigned different access rights to each protected memory region. The Arm M4 core
version in this family does not integrate the Arm Core MPU, which would concurrently
monitor only core-initiated memory accesses. In this document, the term MPU refers to
NXP's system MPU.
13.1.1 MPU Slave Port Assignments
The memory-mapped resources protected by the MPU are:
Table 13-1. MPU Slave Port Assignments
Source MPU Slave Port Assignment Destination
Crossbar slave port 0 MPU slave port 0 Flash Controller
Crossbar slave port 1 MPU slave port 1 SRAM backdoor
Code Bus MPU slave port 2 SRAM_L frontdoor
System Bus MPU slave port 3 SRAM_U frontdoor
Crossbar slave port 3 MPU Slave port 4 QuadSPI
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 201