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49.5.11.4 Pretended Networking mode
This is a special low-power mode used to receive wakeup messages with low power
consumption. This mode can be selected to operate together with Stop mode. Before
entering one of these low-power modes, MCR [PNET_EN] must be asserted. After
entering the low-power mode, CHI subblock is shut down and CAN_PE subblock is kept
active, so that the Rx receive process is still active to filter incoming messages (see
Receive process under Pretended Networking mode
) as defined by the configuration
Pretended Networking Control 1 register (CTRL1_PN)
). Upon detecting a
wakeup event, a Wake Up interrupt is issued to the system.
To enter Pretended Networking mode, FlexCAN must be in normal mode (neither in
Freeze nor in Disable mode). Under Pretended Networking mode, FlexCAN keeps itself
synchronized with the CAN BUS in Stop mode. Then, when Stop mode is requested,
FlexCAN performs the following steps:
• Waits to be in Idle state, or else waits for the third bit of Intermission, and then
checks it to be recessive.
• Sets MCR[LPM_ACK].
• Requests the shutdown of the CHI submodule clock, while keeping the PE
submodule clock active.
FlexCAN can exit Pretended Networking mode by the following ways:
• The CPU removes the Stop Mode request.
• FlexCAN will wait until Bus Idle or third bit of Intermission state to negate
MCR[LPM_ACK].
The above exit ways can be triggered either by the FlexCAN action upon detecting a
wakeup event and issuing the respective interrupt, or by the CPU itself upon being waked
up by another method. In consequence, FlexCAN will wait until the Bus Idle state or
until the third bit of Intermission state to negate MCR[LPM_ACK] and resume Normal
mode. This procedure ensures that FlexCAN will be synchronized to the CAN bus after
exiting Pretended Networking mode. The CPU must wait for MCR[LPM_ACK] to be
negated before performing any access to FlexCAN.
NOTE
For more information about the difference between FD and
non-FD regarding this feature, see
.
Functional description
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1708
NXP Semiconductors
Summary of Contents for MWCT101 S Series
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Page 50: ...Conventions MWCT101xS Series Reference Manual Rev 3 07 2019 50 NXP Semiconductors...
Page 70: ...Aliased bit band regions MWCT101xS Series Reference Manual Rev 3 07 2019 70 NXP Semiconductors...
Page 78: ...Pinout diagrams MWCT101xS Series Reference Manual Rev 3 07 2019 78 NXP Semiconductors...
Page 96: ...WCT101xS safety concept MWCT101xS Series Reference Manual Rev 3 07 2019 96 NXP Semiconductors...
Page 130: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 130 NXP Semiconductors...
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Page 430: ...Functional Description MWCT101xS Series Reference Manual Rev 3 07 2019 430 NXP Semiconductors...
Page 472: ...Application Information MWCT101xS Series Reference Manual Rev 3 07 2019 472 NXP Semiconductors...
Page 528: ...Module clocks MWCT101xS Series Reference Manual Rev 3 07 2019 528 NXP Semiconductors...
Page 634: ...SRAM configuration MWCT101xS Series Reference Manual Rev 3 07 2019 634 NXP Semiconductors...
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Page 992: ...ADC calibration scheme MWCT101xS Series Reference Manual Rev 3 07 2019 992 NXP Semiconductors...
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Page 1726: ...Debug and security MWCT101xS Series Reference Manual Rev 3 07 2019 1726 NXP Semiconductors...
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