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NOTE
There is no remote frame in the CAN FD format. The RTR bit
is replaced by a fixed dominant RRS bit. FlexCAN receives and
transmits remote frames in the Classical CAN format.
49.5.9.5 Overload frames
FlexCAN does transmit overload frames when the following conditions are detected on
the CAN bus:
• Detection of a dominant bit in the first/second bit of Intermission
• Detection of a dominant bit at the 7th bit (last) of End of Frame field (Rx frames)
• Detection of a dominant bit at the 8th bit (last) of Error Frame Delimiter or Overload
Frame Delimiter
49.5.9.6 Time stamp
The value of the free running timer is sampled at the beginning of the Identifier field on
the CAN bus, and is stored at the end of move-in in the TIME STAMP field, providing
network behavior with respect to time.
When CTRL2[TIMER_SRC] is asserted, the free running timer is continuously clocked
by an external time tick.
When CTRL2[TIMER_SRC] is negated, the free running timer is clocked by the
FlexCAN bit-clock, which defines the baud rate on the CAN bus. During a message
transmission/reception, it increments by one for each bit that is received or transmitted.
When there is no message on the bus, it counts using the previously programmed baud
rate.
The free running timer is not incremented during Disable, Stop, and Freeze modes. It can
be reset upon a specific frame reception, enabling network time synchronization. See the
TSYN description in Control 1 register (CTRL1).
Chapter 49 FlexCAN
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors
1691
Summary of Contents for MWCT101 S Series
Page 2: ...MWCT101xS Series Reference Manual Rev 3 07 2019 2 NXP Semiconductors...
Page 42: ...MWCT101xS Series Reference Manual Rev 3 07 2019 42 NXP Semiconductors...
Page 50: ...Conventions MWCT101xS Series Reference Manual Rev 3 07 2019 50 NXP Semiconductors...
Page 70: ...Aliased bit band regions MWCT101xS Series Reference Manual Rev 3 07 2019 70 NXP Semiconductors...
Page 78: ...Pinout diagrams MWCT101xS Series Reference Manual Rev 3 07 2019 78 NXP Semiconductors...
Page 96: ...WCT101xS safety concept MWCT101xS Series Reference Manual Rev 3 07 2019 96 NXP Semiconductors...
Page 130: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 130 NXP Semiconductors...
Page 284: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 284 NXP Semiconductors...
Page 430: ...Functional Description MWCT101xS Series Reference Manual Rev 3 07 2019 430 NXP Semiconductors...
Page 472: ...Application Information MWCT101xS Series Reference Manual Rev 3 07 2019 472 NXP Semiconductors...
Page 528: ...Module clocks MWCT101xS Series Reference Manual Rev 3 07 2019 528 NXP Semiconductors...
Page 634: ...SRAM configuration MWCT101xS Series Reference Manual Rev 3 07 2019 634 NXP Semiconductors...
Page 818: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 818 NXP Semiconductors...
Page 960: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 960 NXP Semiconductors...
Page 992: ...ADC calibration scheme MWCT101xS Series Reference Manual Rev 3 07 2019 992 NXP Semiconductors...
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Page 1726: ...Debug and security MWCT101xS Series Reference Manual Rev 3 07 2019 1726 NXP Semiconductors...
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