NXP Semiconductors MWCT101 S Series, Reference Manual

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(accessing the output of the FIFO as a message buffer). The DMA reading process must
end by reading address 0x8C, which clears IFLAG1[BUF5I] and updates both the FIFO
output with the next message (if FIFO is not empty) and the RXFIR register with the
attributes of the new message. If there are more messages stored in the FIFO,
IFLAG1[BUF5I] will be re-asserted and another DMA request is issued. Otherwise, the
flag remains negated.
NOTE
RXFIR register contents cannot be read after DMA completes
the FIFO read. The IDHIT information is also available in the
C/S word at address 0x080 (see
Rx FIFO structure .
IFLAG1[BUF6I] and IFLAG1[BUF7I] are not used when the DMA feature is enabled.
When FlexCAN is working with DMA, the CPU does not receive any Rx FIFO
interruption and must not clear the related IFLAGs. In addition, the related IMASKs are
not used to mask the generation of DMA requests.
NOTE
For more information about the difference between FD and
non-FD regarding this feature, see
Table 49-3 .
49.5.8.2 Clear FIFO operation
When MCR[RFEN] is asserted, the clear FIFO operation is a feature used to empty FIFO
contents. With MCR[RFEN] asserted the Clear FIFO occurs when the CPU writes one in
IFLAG1[BUF0I]. This operation can only be performed in Freeze mode and is blocked
by hardware in other modes. This operation does not clear the FIFO IFLAGs;
consequently the CPU must service all FIFO IFLAGs before executing the clear FIFO
task.
When Rx FIFO is working with DMA, the clear FIFO operation clears IFLAG1[BUF5I]
and the DMA request is canceled.
CAUTION
Clear FIFO operation does not clear IFLAGs, except when
MCR[DMA] is asserted; in this case only IFLAG1[BUF5I] is
cleared.
49.5.9 CAN protocol related features
This section describes the CAN protocol related features.
Chapter 49 FlexCAN
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1681