NXP Semiconductors MWCT101 S Series, Reference Manual

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Field Function
NOTE: This flag is cleared by the FlexCAN whenever MCR[RFEN] is changed by CPU writes.
The BUF7I flag represents Rx FIFO overflow when MCR[RFEN] is set. In this case, the flag indicates that
a message was lost because the Rx FIFO is full. Note that the flag will not be asserted when the Rx FIFO
is full and the message was captured by a mailbox.
0b - No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO
overflow when MCR[RFEN]=1
1b - MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when
MCR[RFEN]=1
6
BUF6I
Buffer MB6 Interrupt Or Rx FIFO Warning
When MCR[RFEN] is cleared (Rx FIFO disabled), this bit flags the interrupt for MB6.
NOTE: This flag is cleared by the FlexCAN whenever MCR[RFEN] is changed by CPU writes.
The BUF6I flag represents Rx FIFO warning when MCR[RFEN] is set. In this case, the flag indicates
when the number of unread messages within the Rx FIFO is increased to five from four due to the
reception of a new one, meaning that the Rx FIFO is almost full. Note that if the flag is cleared when the
number of unread messages is greater than four, it does not assert again until the number of unread
messages within the Rx FIFO is decreased to be equal to or less than four.
0b - No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO
almost full when MCR[RFEN]=1
1b - MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when
MCR[RFEN]=1
5
BUF5I
Buffer MB5 Interrupt Or Frames available in Rx FIFO
When MCR[RFEN] is cleared (Rx FIFO disabled), this field flags the interrupt for MB5.
NOTE: This flag is cleared by the FlexCAN whenever MCR[RFEN] is changed by CPU writes.
When MCR[RFEN] is set (Rx FIFO enabled), the BUF5I flag represents "Frames available in Rx FIFO"
and indicates that at least one frame is available to be read from the Rx FIFO. When the MCR[DMA] bit is
enabled, this flag generates a DMA request and the CPU must not clear this bit by writing 1 in BUF5I.
0b - No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s)
available in the FIFO, when MCR[RFEN]=1
1b - MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx
FIFO when MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA]
are enabled.
4-1
BUF4TO1I
Buffer MB i Interrupt Or Reserved
When MCR[RFEN] is cleared (Rx FIFO disabled), these bits flag the interrupts for MB4 to MB1.
NOTE: These flags are cleared by the FlexCAN whenever MCR[RFEN] is changed by CPU writes.
The BUF4TO1I flags are reserved when MCR[RFEN] is set.
0b - The corresponding buffer has no occurrence of successfully completed transmission or
reception when MCR[RFEN]=0.
1b - The corresponding buffer has successfully completed transmission or reception when
MCR[RFEN]=0.
0
BUF0I
Buffer MB0 Interrupt Or Clear FIFO bit
When MCR[RFEN] is cleared (Rx FIFO disabled), this field flags the interrupt for MB0. If the Rx FIFO is
enabled, this bit is used to trigger the clear FIFO operation. This operation empties FIFO contents. Before
performing this operation the CPU must service all FIFO related IFLAGs. When MCR[DMA] is enabled
this operation also clears the BUF5I flag and consequently aborts the DMA request. The clear FIFO
operation occurs when the CPU writes 1 in BUF0I. It is only allowed in Freeze mode and is blocked by
hardware in other conditions.
0b - The corresponding buffer has no occurrence of successfully completed transmission or
reception when MCR[RFEN]=0.
Chapter 49 FlexCAN
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1601