NXP Semiconductors MWCT101 S Series, Reference Manual

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• SDA data valid time from SCL negation to SDA update
• SCL hold time when clock stretching is enabled to increase setup time when
sampling SDA externally
• SCL glitch filter time
• SDA glitch filter time
The LPI2C slave imposes the following restrictions on the timing parameters.
• FILTSDA must be configured to greater than or equal to FILTSCL (unless
compensating for board level skew between SDA and SCL).
• DATAVD must be configured less than the minimum SCL low period.
46.4.3.5 Error Conditions
The LPI2C slave can detect the following error conditions:
• Bit error flag will set when the LPI2C slave is driving SDA, but samples a different
value than what is expected.
• FIFO error flag will set due to a transmit data underrun or a receive data overrun. To
eliminate the possibility of underrun and overrun occurring, enable clock stretching.
• FIFO error flag will also set due to an address overrun when RXCFG is set,
otherwise an address overrun is not flagged. To eliminate the possibility of overrun
occurring, enable clock stretching.
The LPI2C slave does not implement a timeout due to SCL and/or SDA being stuck low.
If this detection is required, then the LPI2C master logic should be used and so software
can reset the LPI2C slave when this condition is detected.
46.4.4 Interrupts and DMA Requests
Depending on the specific device, interrupts and DMA requests can be combined in some
ways:
• The LPI2C master and slave interrupts may be combined
• The LPI2C master and slave transmit DMA requests may be combined
• The LPI2C master and slave receive DMA requests may be combined
46.4.4.1 Master mode
The next table lists the master mode sources that can generate LPI2C master interrupts
and LPI2C master transmit/receive DMA requests.
Chapter 46 Low Power Inter-Integrated Circuit (LPI2C)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1463