NXP Semiconductors MWCT101 S Series, Reference Manual

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master and all I2C pins on the bus are at the same voltage. This will configure the
SCL pin as push-pull for every clock except the 9th clock pulse, to allow high speed
mode compatible slaves to perform clock stretching. In this mode, the SDA pin is
tristated for master-receive data bits and master-transmit ACK/NACK bits, and is
configured as push-pull at other times. To avoid the risk of contention when SDA is
push-pull, the pin can be configured for open-drain operation, as part of the device-
specific configuration.
• Push-pull 4-wire support: The push-pull 4-wire configuration separates the SCL
input data and output data into separate pins, and separates the SDA input data and
output data into separate pins. The SCL/SDA pins are used for input data; the SCLS/
SDAS pins are used for output data, with configurable polarity. This simplifies
external connections when connecting the LPI2C to the I2C bus through external
level shifters or discrete components. When using this 4-wire configuration, the
LPI2C master logic and LPI2C slave logic are not able to connect to separate I2C
buses.
46.4.3 Slave Mode
To perform all slave mode transfers on the I2C bus, the LPI2C slave logic operates
independently from the LPI2C master logic.
46.4.3.1 Address Matching
The LPI2C slave can be configured:
• to match one of two addresses, using either 7-bit or 10-bit addressing modes for each
address
• to match a range of addresses in either 7-bit or 10-bit addressing modes
• to match the General Call Address, and generate appropriate flags
• to match the SMBus Alert Address, and generate appropriate flags
• to detect the high speed mode master code, and to disable the digital filters and
output valid delay time until the next STOP condition is detected
After a valid address is matched, the LPI2C slave will automatically perform slave-
transmit or slave-receive transfers until:
• a NACK is detected (unless IGNACK is set)
• a bit error is detected (the LPI2C slave is driving SDA, but a different value is
sampled)
• a (repeated) START or STOP condition is detected
Chapter 46 Low Power Inter-Integrated Circuit (LPI2C)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1461