NXP Semiconductors MWCT101 S Series, Reference Manual, Page: 1389 / 1761

Field Function
• The delay is equal to ( 1) cycles of the LPSPI functional clock divided by the Prescaler
Value TCR[PRESCALE] configuration.
• The minimum delay is 1 cycle.
23-16
PCSSCK
PCS-to-SCK Delay
In master mode: configures the delay from the PCS assertion to the first SCK edge.
• The delay is equal to ( 1) cycles of the LPSPI functional clock divided by the Prescaler
Value TCR[PRESCALE] configuration.
• The minimum delay is 1 cycle.
15-8
DBT
Delay Between Transfers
In master mode:
• Configures the delay from the PCS negation to the next PCS assertion.
• The delay is equal to (DBT + 2) cycles of the LPSPI functional clock divided by the Prescaler
Value TCR[PRESCALE] configuration.
• The minimum delay is 2 cycles.
• Half of the delay occurs before PCS assertion and the other half of the delay occurs after
PCS negation. If the command word is updated between 2 transfers, then the command word
is updated half-way between the PCS negation of the last transfer and PCS assertion of the
next transfer.
• The command word sets which PCS signal is used (of PCS[3:0]}, the polarity/phase of the
SCK signal, and the Prescaler Value.
• Configures the delay from the last SCK edge of a transfer word and the first SCK edge of the next
transfer word, in a continuous transfer.
• The delay is equal to (DBT + 1) cycles of the LPSPI functional clock divided by the Prescaler
Value TCR[PRESCALE] configuration.
• The minimum delay is 1 cycle.
7-0
SCKDIV
SCK Divider
In master mode, the SCK Divider configures the divide ratio of the SCK pin.
• The SCK period is equal to (2) cycles of the LPSPI functional clock divided by the
Prescaler Value TCR[PRESCALE] configuration.
• The minimum SCK period is 2 cycles.
• If the SCK period is an odd number of cycles, then the 1st half of the SCK period will be 1 cycle
longer than the 2nd half of the SCK period.
45.3.1.13 FIFO Control Register (FCR)
45.3.1.13.1 Offset
Register Offset
FCR 58h
Chapter 45 Low Power Serial Peripheral Interface (LPSPI)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1389