NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1374 / 1761

SCLK
MOSI
MISO
SS
SPI
Slave
SCLK
MOSI
MISO
SS
SPI
Slave
SCLK
MOSI
MISO
SS
SPI
Slave
SCLK
MOSI
MISO
SS
Slave select
line
SPI
Master
Each SPI slave
shares the same wired
slave select line
The slaves have to
3 cooperative SPI slaves
SPI master has a
single slave select
pin for all slaves
Daisy-chain SPI bus scheme
cooperate with each other
Figure 45-6. Shared slave select lines (daisy-chain) scheme
Table 45-4. Wiring Scheme Differences
Item Dedicated slave select lines Shared slave select lines (daisy-chain)
slave select lines (pins
on the master device)
• 1 slave select line (pin) for each slave; the
scheme is limited by how many lines (pins)
that the master device can support
• 1 slave select line (pin) for multiple slaves
data flow from master
device to slave devices
• Master sends data directly to the slave that
the data is for; the slaves for whom the
data is not intended, simply ignore the
data; this implies that those slaves could
be asleep (if desired)
• Master sends data and multiple slaves
have to forward the data through the daisy
chain; this implies that all slaves must be
on and awake when the master sends data
to any slave
45.3 Memory Map and Registers
NOTE
Writing a Read-Only (RO) register or reading a Write-Only
(WO) register can cause bus errors. This module will not check
if programmed values in the registers are correct; the
application software must ensure that valid programmed values
are being written.
Memory Map and Registers
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1374 NXP Semiconductors