NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1093 / 1761

40.2.4 Block diagram
This diagram illustrates the major components of the PDB.
Ch n trigger
PDBCH n DLY 0
PDBCH n DLY m
=
Ack 0
Pre-trigger 0
Ch n pre-trigger 0
Ch n pre-trigger m
=
BB[ m ], TOS[ m ]
BB[ 0 ], TOS[ 0 ]
EN[ 0 ]
EN[ m ]
MULT
Ack m
Pre-trigger m
Sequence Error
Detection
ERR[ M - 1:0]
PRESCALER
PDBCNT
PDBMOD
=
CONT
PDBIDLY
=
PDB interrupt
TOE x
=
=
PO y DLY2
PO y DLY1
Pulse
Generation
Pulse-Out y
PDBPOEN[ y ]
Pulse-Out y
Control
logic
PDB counter
Trigger-In 0
SWTRIG
TRIGSEL
trigger_In0
Figure 40-6. PDB block diagram
Chapter 40 Programmable delay block (PDB)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1093