NXP Semiconductors MWCT101 S Series, Reference Manual

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CMPx_C2 field descriptions (continued)
Field Description
16
CH0F
Channel 0 input changed flag. This bit is set if the channel 0 input changed from the last comparison with
the fixed mux port.
15–14
NSAM
Number of sample clocks
For a given channel, this field specifies how many round-robin clock cycles later the sample takes place.
00 The comparison result is sampled as soon as the active channel is scanned in one round-robin clock.
01 The sampling takes place 1 round-robin clock cycle after the next cycle of the round-robin clock.
10 The sampling takes place 2 round-robin clock cycles after the next cycle of the round-robin clock.
11 The sampling takes place 3 round-robin clock cycles after the next cycle of the round-robin clock.
13–8
INITMOD
Comparator and DAC initialization delay modulus.
These values specify the round robin clock cycles used to determine the comparator and DAC initialization
delays specified by the datasheet. For example the initialization delay is 80us and the round robin clock is
100kHz, then INITMOD should be set to 80us/10us = 8.
000000 The modulus is set to 64 (same with 111111).
other values Initialization delay is set to INITMOD × round robin clock period
ACOn The result of the input comparison for channel n . This field stores the latest comparison result of the input
channel n with the fixed mux port. Reading this bit returns the latest comparison result. Writing this field
defines the pre-set state of channel n .
39.9 CMP functional description
The CMP module can be used to compare two analog input voltages applied to INP and
INM. CMPO is high when the non-inverting input is greater than the inverting input, and
is low when the non-inverting input is less than the inverting input. This signal can be
selectively inverted by setting C0[INVT] = 1.
C0[IER] and C0[IEF] are used to select the condition that causes the CMP module to
assert an interrupt to the processor. C0[CFF] is set on a falling edge, and C0[CFR] is set
on a rising edge of the comparator output. The optionally filtered CMPO can be read
directly through C0[COUT].
39.9.1 Initialization
A typical startup sequence is as follows.
Chapter 39 Comparator (CMP)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1075