UM10413
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© NXP B.V. 2011. All rights reserved.
User manual
Rev. 1 — 16 December 2011
48 of 268
NXP Semiconductors
UM10413
MPT612 User manual
10.8.8 PLL and Power-down mode
Power-down mode automatically turns off and disconnects activated PLL(s). Wake-up
from Power-down mode does not automatically restore the PLL settings. This must be
done in software. Typically, a routine to activate the PLL, wait for lock, and then connect
the PLL can be called at the beginning of any interrupt service routine that might be called
due to the wake-up. It is important not to attempt to restart the PLL by simply feeding it
when execution resumes after a wake-up from Power-down mode. This enables and
connects the PLL at the same time, before PLL lock is established.
10.8.9 PLL frequency calculation
The PLL equations use the following parameters:
The PLL output frequency (when the PLL is both active and connected) is given by:
CCLK = M
f
osc
or CCLK = f
CCO
/ (2
P)
The CCO frequency can be computed as:
f
CCO
= CCLK
2
P or f
CCO
= f
osc
M
2
P
The PLL inputs and settings must meet the following requirements:
•
f
osc
is in the range 10 MHz to 25 MHz.
•
CCLK is in the range 10 MHz to f
max
(the maximum allowed frequency for the
MPT612 - embedded in and determined by the system MPT612).
•
f
CCO
is in the range 156 MHz to 320 MHz.
10.8.10 Procedure for determining PLL settings
If a particular application uses the PLL, its configuration can be determined as follows:
1. Choose the desired processor operating frequency (CCLK). This can be based on
processor throughput requirements, such as the need to support a specific set of
UART baud rates, and so on, Bear in mind that peripheral devices can be running
from a lower clock than the processor (see
Section 10.11 “APB Divider” on page 54
).
2. Choose an oscillator frequency (f
osc
). CCLK must be the whole (non-fractional)
multiple of f
osc
.
Table 49.
PLL Feed register (PLLFEED - address 0xE01F C08C) bit description
Bit
Symbol
Description
Reset
value
7:0
PLLFEED
PLL feed sequence must be written to this register for changes to PLL
configuration and control register to take effect
0x00
Table 50.
Parameters determining PLL frequency
Element
Description
f
osc
frequency of crystal oscillator/external oscillator
f
CCO
frequency of PLL current controlled oscillator
CCLK
PLL output frequency (also processor clock frequency)
M
PLL multiplier value from MSEL bits in register PLLCFG
P
PLL divider value from PSEL bits in register PLLCFG
