NXP Semiconductors MPC5644A, Reference Manual, Page: 940 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
940 Freescale Semiconductor
Shift register operations
SR can be used as a general purpose register and it can easily shift-right its contents, combined or not to
post-ALU shift operations. If field SRC (1 bit) in microcode is 0, SR will shift its contents 1 bit to the right
according to the algorithmic description below. SR shifting operation depends also on SHF or ALUOP
fields. ALUOP and SHF never exist both on the same microinstruction format.
SR Operation :
SR[22:0] = SR[23:1];
if SHF == “01” or ALUOP == “10110” then
SR[23] = ALU_OUT[0];
else
SR[23] = 0;
endif;
Post-ALU shift operations
Post-ALU shift can be selected by SHF field (2 bits) or by some specific ALUOP field values. SHF and
ALUOP fields are never both available in the same microinstruction format. When selecting post-ALU
shift operation using ALUOP field, ALU will always add the sources before shifting the result.
Carry flag is only updated when CCS or CCSV[1:0] fields allow it (see Section 24.5.9.2.3, Flags sampling
control ). Algorithmic descriptions of post-ALU shift operations are presented in Section 24.5.8.2.2, ALU
ADD Operation with and without shifting .
24.5.9.2.7 Conditional ALU/MDU operation execution
The 3-bit field AS/CE allows conditional execution of arithmetic operation, as shown in Table 24-90 . The
same field can also be used for overriding the size of A-Source (see Section 24.5.9.2.8, A-Source size
override ).
Table 24-88. Shift Register Control – SRC
SRC Meaning
0 shift right SR 1 bit
1 no shift
Table 24-89. Post-ALU shift operation
Post ALU operation SHF
1
1
ALU performs AS+BS before shift/rotate for all SHF values.
ALUOP
shift left (1 bit) 00 10101
shift right (1 bit) 01 10110
rotate right (1 bit) 10 10111
no shift/rotate 11 any other
2
2
Some ALUOP combinations perform shift/rotate, but not using the Post-ALU Shifter (see
Table 24-94 )