NXP Semiconductors MPC5644A, Reference Manual, Page: 798 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
798 Freescale Semiconductor
24.4.6.6 ETPU_CDTRER – eTPU Channel Data Transfer Request Enable Register
Data Transfer request enable (see Section 24.5.2.2, Interrupts and data transfer requests ) from all channels
are grouped in ETPU_CDTRER. These bits are mirrored from the Channel Configuration registers (see
Section 24.4.7.1, ETPU_CxCR – eTPU Channel x Configuration Register ).
Figure 24-18. ETPU_CDTRER Register
Offset: eTPU_A: eTP 0x250; eTPU_B: eTP 0x254 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R DTR
E
31
DTR
E
30
DTR
E
29
DTR
E
28
DTR
E
27
DTR
E
26
DTR
E
25
DTR
E
24
DTR
E
23
DTR
E
22
DTR
E
21
DTR
E
20
DTR
E
19
DTR
E
18
DTR
E
17
DTR
E
16
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R DTR
E
15
DTR
E
14
DTR
E
13
DTR
E
12
DTR
E
11
DTR
E
10
DTR
E
9
DTR
E
8
DTR
E
7
DTR
E
6
DTR
E
5
DTR
E
4
DTR
E
3
DTR
E
2
DTR
E
1
DTR
E
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Table 24-28. ETPU_CDTRER field description
Field Description
0-31 DTREx—Channel x Data Transfer Request Enable
1: Data Transfer request enabled for channel x.
0: Data Transfer request disabled for channel x.
For details about interrupts see Section 24.5.9.3.10, Channel interrupt and data transfer requests .