NXP Semiconductors MPC5644A, Reference Manual, Page: 749 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 749
Figure 24-2. eTPU engine block diagram
eTPU engines 1 and 2 are sometimes called eTPU 1 and eTPU 2 throughout this document.
24.2.1.1.1 Time bases
Two 24-bit counters TCR1 and TCR2 provide reference time bases for all match and input capture events.
Prescalers for both time bases are controlled by the Host CPU through bit fields in the eTPU engine
configuration registers. The eTPU is able to export/import time to/from TCR1 or TCR2 in accordance to
the Red Line bus specification.
The clock for each of TCR1 and TCR2 clock can be independently derived from the system clock or from
an external input via the TCRCLK clock pin. In addition, the TCR2 timebase can be derived from special
angle-clock hardware which enables implementing angle-based functions. This feature is added to support
advanced angle based engine control applications.
For further details refer to Section 24.5.6, Time Bases .
TCR1
TCR2/
MICROENGINE
CODE
IPI
HOST
INTERFACE
CHANNEL
CONTROL
TIME BASE
CONFIGURATION
ENGINE
CONFIGURATION
SCHEDULER
CONTROL AND DATA
CONTROL
TIMER
CHANNELS
CHANNEL 0
CHANNEL 1
CHANNEL 31
CH
A
NNEL
CONTROL
TCRCLK
PIN
MDU
ANGLE COUNT
SERVICE REQUESTS
Red Line
INTERFACE
Red Line
(SCM)
PARAMETER
RAM
SHARED
(SPRAM)
SHARED
MEMORY
FETCH and
DECODE
EXECUTION
DA
T
A
CODE
DarkBlue
Line
UNIT
DEBUG
INTERFACE
to NDEDI
CONTROL
and DATA
IPI
Indigo
Line
IPI
SkyBlue,
Green
IPI
Purple
Line
(PINS)
Lines