NXP Semiconductors MPC5644A, Reference Manual, Page: 734 / 1735

Reaction Module (REACM)
MPC5644A Microcontroller Reference Manual, Rev. 6
734 Freescale Semiconductor
NOTE
In order to define RANGE_PWD value it is required to consider that the
Hold-off timer already measured MIN_PWD, thus actually the maximum
allowed pulse width = (M RANGE_PWD). In other words,
RANGE_PWD = (maximum allowed pulse width

MIN_PWD).
IF MIN_PWD = 0x00 or RANGE_PWD = 0x00 no pulse width is
performed.
The CHSR SCDF flag does not set if the pulse was finished by disabling the modulation (i.e., eTPU
channel = 0 or SWMC = 0) or by disabling the channel, CHEN = 00, even if it ended shorter than
MIN_PWD. However this flag can set in some situations that really indicates a short pulse detection but
it is the result of some internal condition of the reaction module. The known situations are listed below:
• when the shared timer error occurs (TAER flag is set), a narrow pulse can be generated and SCDF
flag is set.
• when the CHCR CHOFF bit is set, a narrow pulse can be generated and SCDF flag is set.
The CHSR OCDF flag only sets when the channel is enabled (CHEN not null) and the eTPU channel
signal or SWMC is active too. However, the OCDF flag can set in some cases when the CHOFF bit is set.
In this case, this OCDF flag should be disregarded because it is a false indication of the detector.
There can be a conflict of resource allocation if the Hold-off timer is used as the timer for the sequencer
mode SM = 10. In this case it is not possible to detected minimum or maximum pulse widths thus the
monitored modulation is deactivated. Which means the use of the Hold-off timer in the sequence mode has
precedence over the monitored modulation. This configuration is not considered an error though, since it
may occur during one of the phases of a modulation cycle and return to a sequence mode where the
monitored modulation is possible. Thus no flags will be set to signal this conflict condition.
23.7 DMA support
The Reaction Module provides supports for one DMA channel per Reaction Channel. The DMA request
signal is controlled by the DMAEN bit in the Channel Configuration Register
Figure 23-9 and by the
DMA bit in the Modulation Control Word, Figure 23-18 . If the DMAEN = 1 and the DMA = 1 then a
DMA request is issued by the Reaction Channel. Note that the DMA request is deaserted if the DMA done
signal is asserted even though the channel is still pointing to the same Modulation Control Word that
generated the DMA request. In order for a new DMA request be issued after the DMA done is issued, the
Reaction Channel must access a new Modulation Control Word or execute a new modulation cycle
controlled by the timer input signal.
Figure 23-34 shows the DMA protocol executed by the Reaction
Channel. The DMA request signal is asserted when the Modulation Word 1 is executed by the channel.
This signal remains asserted until a DMA done signal is issued by the DMA controller.