NXP Semiconductors MPC5644A, Reference Manual, Page: 686 / 1735

Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5644A Microcontroller Reference Manual, Rev. 6
686 Freescale Semiconductor
22.5.4 Global clock prescaler submodule (GCP)
The GCP divides the system clock to generate a clock for the CPs of the channels. The main clock signal
is prescaled by the value defined in the GPRE[0:7] bits in the EMIOS_MCR. The global prescaler is
enabled by setting bit EMIOS_MCR[GPREN] and can be stopped at any time by clearing this bit, thereby
stopping the internal counters in all the channels.
In order to ensure safe working and avoid glitches the following steps must be performed whenever any
update in the prescaling rate is desired:
1. Write ‘0’ at bit EMIOS_MCR[GPREN], thus disabling global prescaler.
2. Write the desired value for prescaling rate at GPRE[0:7] bits in EMIOS_MCR.
3. Enable global prescaler by writing ‘1’ at bit EMIOS_MCR[GPREN].
The prescaler is not disabled during either freeze state or negated GTBE input.
22.5.4.1 Effect of freeze on the GCP
When bit EMIOS_MCR[FRZ] is set and the module is in debug mode, the operation of GCP submodule
is not affected, that is, there is no freeze function in this submodule.
22.6 Initialization/Application information
On resetting the eMIOS200 the channels enter GPIO input mode.
22.6.1 Considerations
Before changing an operating mode, the UC must be programmed to GPIO mode and EMIOS_CADR[n]
and EMIOS_CBDR[n] registers must be updated with the correct values for the next operating mode. Then
the EMIOS_CCR[n] can be written with the new operating mode. If a channel is changed from one mode
to another without performing this procedure, the first operation cycle of the selected time base can be
random, that is, matches can occur in random time if the contents of EMIOS_CADR[n] or
EMIOS_CBDR[n] were not updated with the correct value before the time base matches the previous
contents of EMIOS_CADR[n] or EMIOS_CBDR[n].
When interrupts are enabled, the software must clear the FLAG bits before exiting the interrupt service
routine.
22.6.2 Application information
Correlated output signals can be generated by all output operation modes. Bits OU[n] of the
EMIOS_OUDR can be used to control the update of these output signals.
In order to guarantee that the internal counters of correlated channels are incremented in the same clock
cycle, the internal prescalers must be set up before enabling the global prescaler. If the internal prescalers
are set after enabling the global prescaler, the internal counters may increment in the same ratio but at a
different clock cycle.