NXP Semiconductors MPC5644A, Reference Manual, Page: 675 / 1735

Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 675
Figure 22-30. OPWFMB A1 and B1 match to Output Register Delay
Figure 22-31 describes the generated output signal if A1 is set to 0x0. Since the counter does not reach
zero in this mode, the channel internal logic infers a match as if A1 = 0x1 with the difference that in this
case, the posedge of the match signal is used to trigger the output pin transition instead of the negedge used
when A1 = 0x1. Note that A1 posedge match signal from cycle
n+1 occurs at the same time as B1 negedge
match signal from cycle n . This allows using the A1 posedge match to mask the B1 negedge match when
they occur at the same time. The result is that no transition occurs on the output flip-flop and a 0% duty
cycle is generated.
8
1
4
match A1 negedge detection
5
A1 value
0x000004
A1 match
A1 match negedge detection
output pin
EDPOL = 0
EMIOSCNT
TIME
match B1 negedge detection
B1 match
B1 match negedge detection
B1 value
0x000008
system clock
prescaler
Prescaler ratio = 2