NXP Semiconductors MPC5644A, Reference Manual, Page: 666 / 1735

Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5644A Microcontroller Reference Manual, Rev. 6
666 Freescale Semiconductor
Figure 22-18. SAOC example with flag behavior
22.5.1.1.4 Input pulse width measurement (IPWM) mode
The IPWM mode (MODE[0:6] = 0000100) allows the measurement of the width of a positive or negative
pulse by capturing the leading edge on register B1 and the trailing edge on register A2. Successive captures
are done on consecutive edges of opposite polarity. The leading edge sensitivity (that is, pulse polarity) is
selected by EDPOL bit in the EMIOS_CCR[n]. Registers EMIOS_CADR[n] and EMIOS_CBDR[n]
return the values in registerS A2 and B1, respectively.
The capture function of register A2 remains disabled until the first leading edge triggers the first input
capture on register B2. When this leading edge is detected, the count value of the selected time base is
latched into register B2; the FLAG bit is not set. When the trailing edge is detected, the count value of the
selected time base is latched into register A2 and, at the same time, the FLAG bit is set and the content of
register B2 is transferred to register B1 and to register A1.
If subsequent input capture events occur while the corresponding FLAG bit is set, registers A2, B1 and A1
will be updated with the latest captured values and the FLAG will remain set. Registers EMIOS_CADR[n]
and EMIOS_CBDR[n] return the value in registers A2 and B1, respectively.
In order to guarantee coherent access, reading EMIOS_CADR[n] forces B1 be updated with the content
of register A1. At the same time transfers between B2 and B1 are disabled until the next read of
EMIOS_CBDR[n]. Reading EMIOS_CBDR[n] forces B1 be updated with A1 register content and
re-enables transfers from B2 to B1, to take effect at the next trailing edge capture. Transfers from B2 to
A1 are not blocked at any time.
The input pulse width is calculated by subtracting the value in B1 from A2.
Figure 22-19 shows how the channel can be used for input pulse width measurement.
selected counter bus 0x0 0x2
FLAG set event
A2 value
1
0x1
output flip-flop
Note: 1. CADR[n] <= A2
0x0 0x2 0x1 0x2 0x0 0x1 0x1
FLAG pin/register
FLAG clear
EDSEL = 1
System Clock
A1 match
EDPOL = x