NXP Semiconductors MPC5644A, Reference Manual, Page: 634 / 1735

Boot Assist Module (BAM)
MPC5644A Microcontroller Reference Manual, Rev. 6
634 Freescale Semiconductor
Figure 21-8. Start address, VLE bit and download size in bytes
The start address defines where the received data will be stored and where the device will branch
after the download is finished. The two least significant bits of the start address are ignored by the
BAM program, such that the loaded code should be 32-bit word aligned.
The length defines how many data bytes to be loaded.
The VLE mode bit instructs the device to program MMU entries 1–3 with VLE attribute. If it is 1,
the downloaded code must be compiled to VLE instructions, if it is 0 the code contains Power
instructions.
3. Download data.
Each byte of data received is stored in the device memory, starting at the address specified in the
previous protocol step, and incrementing through memory until the number of bytes of data
received and stored in memory matches the number specified in the previous protocol step.
BAM program buffers incoming data, collecting up to eight bytes. The buffered data is written to
the RAM with 64-bit writes to prevent ECC errors, which may happen if the device RAM is
protected by 64-bit ECC code.
Once the buffered data is written to the RAM the BAM program refreshes the SWT watchdog.
NOTE
Only system RAM supports 64-bit writes; therefore, attempting to
download data to other RAM apart from system RAM will cause errors.
If the start address of the downloaded data is not on an 8-byte boundary, the
BAM will write 0x0 to the memory locations from the proceeding 8-byte
boundary to the start address (maximum 4 bytes). The BAM also writes 0x0
to all memory locations from the last byte of data downloaded to the
following 8 byte boundary (maximum 7 bytes) and additional 8 zero bytes
to prevent possible ECC errors may be caused by the CPU prefetching.
4. Switch to the loaded code.
The BAM program waits for the last echo message transmission to complete, then the active
communication controller is disabled. Its pins revert to GPIO inputs.
To provide compatibility with older devices, the BAM writes the core time base registers (TBU
and TBL) with 0x0 and enables the core watchdog to cause a reset after a time-out period of
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
START_ADDRESS[0:15]
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
START_ADDRESS[16:31]
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
VLE CODE_LENGTH[0:14]
48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
CODE_LENGTH[15:30]