NXP Semiconductors MPC5644A, Reference Manual, Page: 607 / 1735

System Timer Module (STM)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 607
Chapter 19
System Timer Module (STM)
19.1 Information Specific to This Device
This section presents device-specific parameterization and customization information not specifically
referenced in the remainder of this chapter.
19.1.1 Device-Specific Features
• One 32-bit up counter with 8-bit prescaler
• Four 32-bit compare channels
• Independent interrupt source for each channel
• Counter can be stopped in debug mode
19.2 Introduction
19.2.1 Overview
The System Timer Module (STM) is a 32-bit timer designed to support commonly required system and
application software timing functions. The STM includes a 32-bit up counter and four 32-bit compare
channels with a separate interrupt source for each channel. The counter is driven by the system clock
divided by an 8-bit prescale value (1 to 256).
19.2.2 Modes of operation
The STM supports two device modes of operation: normal and debug. When the STM is enabled in normal
mode, its counter runs continuously. In debug mode, operation of the counter is controlled by the FRZ bit
in the STM_CR register. If the FRZ bit is set, the counter is stopped in debug mode, otherwise it continues
to run.
19.3 External signal description
The STM does not have any external interface signals.
19.4 Memory map and register definition
The STM programming model has fourteen 32-bit registers. The STM registers can only be accessed using
32-bit (word) accesses. Attempted references using a different size or to a reserved address generates a bus
error termination.
19.4.1 Memory map
The STM memory map is shown in Table 19-1 .