NXP Semiconductors MPC5644A, Reference Manual, Page: 600 / 1735

Error Correction Status Module (ECSM)
MPC5644A Microcontroller Reference Manual, Rev. 6
600 Freescale Semiconductor
18.4.4.9 RAM ECC Syndrome Register (ECSM_PRESR)
The ECSM_PRESR is an 8-bit register for capturing the error syndrome of the last, properly-enabled ECC
event in the RAM memory. Depending on the state of the ECC Configuration Register, an ECC event in
the RAM causes the address, attributes and data associated with the access to be loaded into the
ECSM_REAR, ECSM_PRESR, ECSM_REMR, ECSM_REAT and ECSM_REDR registers, and the
appropriate flag (RNCE) in the ECC Status Register to be asserted.
The ECSM_PRESR can only be read from the IPS programming model; any attempted write is ignored.
Register address: ECSM Base + 0x0060 (0xFFF4_0060)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R REAR[31:16]
W
Reset — — — — — — — — — — — — — — — —
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R REAR[15:0]
W
Reset — — — — — — — — — — — — — — — —
= Unimplemented
Figure 18-11. RAM ECC Address Register (ECSM_REAR)
Table 18-13. ECSM_REAR field description
Name Description
0–31
REAR[31:0]
RAM ECC Address Register
This 32-bit register contains the faulting access address of the last, properly-enabled RAM ECC
event.
Register address: ECSM Base + 0x0065 (0xFFF4_0065)
0 1 2 3 4 5 6 7
R PRESR[7:0]
W
Reset — — — — — — — —
= Unimplemented
Figure 18-12. RAM ECC Syndrome Register (ECSM_PRESR)