NXP Semiconductors MPC5644A, Reference Manual, Page: 585 / 1735

Error Correction Status Module (ECSM)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 585
18.4.2 Miscellaneous Wakeup Control Register (ECSM_MWCR)
Implementation of low-power sleep modes and exit from these modes via an interrupt require
communication between the ECSM, the interrupt controller (INTC) and external logic typically associated
with phase-locked loop clock generation circuitry. The Miscellaneous Wakeup Control Register
(ECSM_MWCR) provides an 8-bit register controlling entry into these types of low-power modes as well
as definition of the interrupt level needed to exit the mode.
The following sequence of operations is generally needed to enable this functionality. Note that the exact
details are likely to be system-specific.
1. The processor core loads the appropriate data value into the ECSM_MWCR, setting the ENBWCR
bit and the desired interrupt priority level.
2. At the appropriate time, the processor ceases execution. The exact mechanism varies by processor
core. In some cases, a processor-is-stopped status is signaled to the ECSM and external logic. This
assertion, if properly enabled by ECSM_MWCR[ENBWCR], causes the ECSM output signal
“enter_low_power_mode” to be set. This, in turn, causes the selected external, low-power mode,
to be entered, and the appropriate clock signals disabled. In most implementations, there are
multiple low-power modes, where the exact clocks to be disabled vary across the different modes.
3. After entering the low-power mode, the interrupt controller enables a special combinational logic
path which evaluates all unmasked interrupt requests. The device remains in this mode until an
event which generates an unmasked interrupt request with a priority level greater than the value
programmed in the ECSM_MWCR[PRILVL] occurs.
4. Once the appropriately-high interrupt request level arrives, the interrupt controller signals its
presence, and the ECSM responds by asserting an “exit_low_power_mode” signal.
5. The external logic senses the assertion of the “exit” signal, and re-enables the appropriate clock
signals.
Register address: ECSM Base + 0x000F (0xFFF4_000F)
0 1 2 3 4 5 6 7
R POR OFPLR 0 0 0 0 0 0
W
Reset 1 0 0 0 0 0 0 0
= Unimplemented
Figure 18-1. Miscellaneous Reset Status Register (ECSM_MRSR)
Table 18-2. ECSM_MRSR field description
Name Description
0
POR
Power-On Reset
1 = Last recorded event was caused by a power-on reset (based on a device input signal)
1
OFPLR
Device Input Reset
1 = Last recorded event was a reset caused by a device input reset.