NXP Semiconductors MPC5644A, Reference Manual, Page: 47 / 1735

Introduction
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 47
• Short latency time due to an arbitration scheme for high-priority messages
• Low power mode, with programmable wake-up on bus activity
1.4.18 FlexRay
The MPC5644A includes one dual-channel FlexRay module that implements the FlexRay
Communications System Protocol Specification, Version 2.1 Rev A. Features include:
• Single channel support
• FlexRay bus data rates of 10 Mbit/s, 8 Mbit/s, 5 Mbit/s, and 2.5 Mbit/s supported
• 128 message buffers, each configurable as:
— Receive message buffer
— Single buffered transmit message buffer
— Double buffered transmit message buffer (combines two single buffered message buffer)
• 2 independent receive FIFOs
— 1 receive FIFO per channel
— Up to 255 entries for each FIFO
• ECC support
1.4.19 System timers
The system timers include two distinct types of system timer:
• Periodic interrupts/triggers using the Periodic Interrupt Timer (PIT)
• Operating system task monitors using the System Timer Module (STM)
1.4.19.1 Periodic interrupt timer (PIT)
The PIT provides five independent timer channels, capable of producing periodic interrupts and periodic
triggers. The PIT has no external input or output pins and is intended to provide system ‘tick’ signals to
the operating system, as well as periodic triggers for eQADC queues. Of the five channels in the PIT, four
are clocked by the system clock and one is clocked by the crystal clock. This one channel is also referred
to as Real-Time Interrupt (RTI) and is used to wake up the device from low power stop mode.
The following features are implemented in the PIT:
• 5 independent timer channels
• Each channel includes 32-bit wide down counter with automatic reload
• 4 channels clocked from system clock
• 1 channel clocked from crystal clock (wake-up timer)
• Wake-up timer remains active when System STOP mode is entered; used to restart system clock
after predefined time-out period
• Each channel optionally able to generate an interrupt request or a trigger event (to trigger eQADC
queues) when timer reaches zero