NXP Semiconductors MPC5644A, Reference Manual, Page: 395 / 1735

System Integration Unit (SIU)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 395
16.6.8 DMA/Interrupt Request Select Register (SIU_DIRSR)
The DMA/Interrupt Request Select Register allows selection between a DMA or interrupt request for
events on the IRQ[0:3] inputs.
Figure 16-8. DMA/Interrupt Request Select Register (SIU_DIRSR)
Table 16-11. SIU_DIRER field description
Field Description
NMI_SEL Non-Maskable Interrupt / Critical Interrupt Selection x
The SIU generates two specific sources of interrupt to the core. One of them is defined as the critical
interrupt (IVOR0 core exception) and the other is defined as the non-maskable interrupt (NMI) (IVOR1
core exception). The NMI_SEL bit selects which exception will be generated by the external NMI pin.
This bit is cleared only by a reset.
1: Critical interrupt (IVOR0) is enabled
0: NMI (IVOR1) is enabled
NMI_SEL0 Non-Maskable Interrupt / Critical Interrupt Selection x
The SIU generates two specific sources of interrupt to the core. One of them is defined as the critical
interrupt (IVOR0 core exception) and the other is defined as the non-maskable interrupt (NMI) (IVOR1
core exception). The NMI_SEL0 bit selects which exception will be generated by the SWT interrupt.
This bit is cleared only by a reset.
1: Critical interrupt (IVOR0) is enabled
0: NMI (IVOR1) is enabled
EIRE x External DMA/Interrupt Request Enable x
This bit enables the assertion of a DMA or the interrupt request from the SIU to the interrupt controller
when an edge triggered event occurs on the IRQ
x inputs.
1: External interrupt request is enabled
0: External interrupt request is disabled
SI 0x1C
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0 0 0 0 0 0 0 0 0 0 0 0
DI
R
S
3
DI
R
S
2
DI
R
S
1
DI
R
S
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Table 16-12. SIU_DIRSR field description
Field Description
DIRS x DMA/Interrupt Request Select x
This bit selects between a DMA or interrupt request when an edge triggered event occurs on the
corresponding IRQ
x input.
1: DMA request is selected (on this device these DMA connections do not exist, causing the interrupt
to be inhibit)
0: Interrupt request is selected