NXP Semiconductors MPC5644A, Reference Manual, Page: 394 / 1735

System Integration Unit (SIU)
MPC5644A Microcontroller Reference Manual, Rev. 6
394 Freescale Semiconductor
16.6.7 DMA/Interrupt Request Enable Register (SIU_DIRER)
The DMA/Interrupt Request Enable Register allows the assertion of a DMA or interrupt request if the
corresponding flag bit is set in
Section 16.6.6, External Interrupt Status Register (SIU_EISR) . The
External Interrupt Request Enable bits enable the interrupt or DMA request. There is only one interrupt
request from the SIU to the interrupt controller. The EIRE bits allow selection of which External Interrupt
Request Flag bits cause assertion of the one interrupt request signal.
Figure 16-7. DMA/Interrupt Request Enable Register (SIU_DIRER)
SWT Software Watch Dog Timer Interrupt Flag, from platform
This bit is set when a SWT interrupt occurs on the platform.
1: An SWT event has occurred
0: No SWT event has occurred
EIF x External Interrupt Request Flag x
This bit is set when an edge triggered event occurs on the corresponding IRQ x input.
1: An edge triggered event has occurred on the corresponding IRQ x input
0: No edge triggered event has occurred on the corresponding IRQ x input
SI 0x18
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
NMI_SEL
1
1
This bit is cleared only by a reset.
0 0 0 0 0 0 0
NMI_SEL0
1
0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
EIRE15 EIRE14 EIRE13 EIRE12 EIRE11 EIRE10
EIRE
9
EIRE
8
EIRE
7
0
EIRE
5
EIRE
4
EIRE
3
EIRE
2
EIRE
1
EIRE
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Table 16-10. SIU_EISR field description (continued)
Field Description